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zydis
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272 Commits

Author SHA1 Message Date
flobernd 5d6c58ad1c Fixed `ZydisISAExt` enum 2017-09-10 20:43:01 +02:00
flobernd fec4116ad6 Minor refactorings and bugfixes 
- Added the `ZYDIS_ATTRIB_HAS_MVEX` attribute
- Updated attribute macro values
- Changed size of `ZydisDecodeGranularity` from 32-bit to 8-bit
 2017-09-09 14:16:54 +02:00
flobernd 5914abc0be Tables fixes and more meta-info 
- Added exception-class meta-info
- Added CMake option for shared-libraries
- Fixed some instruction-definitions
- Updated VersionInfo.rc
 2017-09-06 17:05:05 +02:00
flobernd fafa93d40b Internal refactorings and new meta-info 
- Imported meta-info from Intel XED
- Added instruction-category meta-info to the `ZydisDecodedInstruction` struct
- Added isa-set meta-info to the `ZydisDecodedInstruction` struct
- Added isa-extension meta-info to the `ZydisDecodedInstruction` struct
 2017-09-05 17:35:23 +02:00
flobernd 14d87fda8b Fixed wrong return value of `ZydisFormatterSetHook` 2017-08-23 20:40:57 +02:00
flobernd f89398877d Merge branch 'master' into develop 2017-08-15 14:33:07 +02:00
flobernd 74484aec2e Removed trailing whitespace after mnemonic for instructions without visible operands 2017-08-14 17:10:24 +02:00
Joel Höner c0fd657f15 Merged internal encoder AVX/REX structs 
- It was pretty redundant before
  - Required unnecessary routing logic
  - Minor decrease of required stack memory
- Added `ZydisEmitMVEX` and generally more MVEX support
 2017-08-03 02:04:39 +02:00
Joel Höner 9437e89006 More encoder progress 2017-08-03 01:25:25 +02:00
Joel Höner 87394ef4da Added basic support for Windows kernel drivers 
- Manual typedefs for fixed width int types
- Custom `vsnprintf` function
- Disable ZYDIS_ASSERT and ZYDIS_UNREACHABLE
 2017-07-28 22:25:20 +02:00
Joel Höner 5ac595eb72 Major rework of encoder context design 
- Split into various smaller structs
- Only hand functions parts they actually need
 2017-07-28 03:13:30 +02:00
Joel Höner 9152714865 Fixed encoder IMM size derivation 2017-07-28 02:26:52 +02:00
Joel Höner 4140db6c1f Encoder progress, ZYDIS_UNREACHABLE for MSVC 2017-07-28 00:37:52 +02:00
flobernd 03ef968413 `REX.R` and `REX.B` is ignored for non-GPR/VR/CR/DR registers 2017-07-26 18:17:59 +02:00
flobernd cde97dca36 Fixed a bug that caused the formatter to falsely print a `{sae}` decorator in some cases 2017-07-25 14:58:17 +02:00
flobernd 7434bea839 Fixed some `EVEX` instruction-definitions 
- A bug in the table generator caused inverted conditions regarding zero-mask support for some `EVEX` instructions
 2017-07-25 14:30:32 +02:00
flobernd 341f3866c3 Various changes to the instruction-definitions and decoder/encoder-tables 2017-07-19 18:43:59 +02:00
flobernd e76c3d64c3 Added missing instructions to the encoder-table 2017-07-18 22:38:56 +02:00
flobernd 54d3836256 Minor improvements to the instruction-formatter 2017-07-15 03:39:48 +02:00
flobernd 9e15ecc5f1 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-07-14 22:56:06 +02:00
flobernd 53e89b0800 Replaced `EVEX.z` filter by `acceptsZeroMask` attribute 2017-07-14 22:54:22 +02:00
Joel Höner 58fffa4e71 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-07-12 23:57:25 +02:00
Joel Höner ebd1e18d0f More work in the operand encoding derivation logic 2017-07-12 23:57:20 +02:00
flobernd 59fa404919 Added detailed information about accessed CPU-flags 2017-07-12 17:48:02 +02:00
flobernd 13a2858210 Added hidden R/E/FLAGS register operands 2017-07-12 15:44:47 +02:00
flobernd 682c647eb6 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-07-11 22:22:33 +02:00
flobernd bb1708daaf Preparations for the CPU-flag info feature 2017-07-11 18:51:54 +02:00
Joel Höner 743048852c More encoder progress 2017-07-10 23:43:52 +02:00
Joel Höner 3498a33944 More clean-up in the encoder 2017-07-10 14:34:25 +02:00
flobernd 8fa80f0b86 Minor bugfixes and improvement of the encoder-table 
- Fixed scale-factor of memory operands, if SIB byte is used
- Fixed operand-encoding missing for some operands
- Added operand-size and address-size filters to the encoder-table
 2017-07-09 18:06:43 +02:00
flobernd 5c07598a2d Improved encoder-table 2017-07-06 21:49:38 +02:00
Joel Höner 6bd79283e0 Fixed encoder header 2017-07-06 13:12:43 +02:00
Joel Höner 610d08960b Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 
# Conflicts:
#	CMakeLists.txt
 2017-07-06 08:17:38 +02:00
Joel Höner 41776bac29 Updated encoder to a lot of previous refactorings 2017-07-06 08:07:22 +02:00
flobernd df2dbd9109 Refactorings 
- Renamed Types.h to CommonTypes.h
- Splitted DecoderTypes.h into SharedTypes.h and DecoderTypes.h
- Splitted InstructionTable.h into SharedData.h and DecoderData.h
- Implemented `ZydisGetEncodableInstructions` in EncoderData.h
- Some internal changes to the data-tables
 2017-07-06 00:34:36 +02:00
flobernd f8f928a4a8 Added number of decoded instructions to the performance-test tool output 2017-07-05 16:28:16 +02:00
flobernd 428da82416 Added `ZYDIS_ATTRIB_IS_PRIVILEGED` 2017-07-05 13:47:54 +02:00
flobernd 34a0572948 Refactorings 2017-07-05 13:33:59 +02:00
flobernd 8a626388ae Improved formatting of decorators 2017-07-04 19:02:11 +02:00
flobernd af0c6c8cac Removed EVEX/MVEX compressed 8-bit displacement scale-factor from the public interface (for now) 2017-07-04 16:26:03 +02:00
flobernd b9cf56af4d Refactorings 2017-07-04 16:10:21 +02:00
flobernd bbf8b1193b Added performance test 2017-07-03 21:10:04 +02:00
flobernd 87c9155207 Refactorings 2017-07-03 17:36:03 +02:00
flobernd 6ce34bd141 Added error-condition for illegal LOCK-prefixes 2017-07-03 17:02:32 +02:00
Joel Höner 7ba6ea0596 Moved private headers to `src` directory 2017-07-03 04:16:38 +02:00
flobernd 38c67d2a85 Refactorings 2017-07-03 03:14:01 +02:00
flobernd ad8e5ce6a9 Minor refactorings 2017-07-01 01:10:03 +02:00
flobernd 392c36c85f Fixed decoding of MASK register (again) 2017-06-29 21:12:22 +02:00
flobernd c2a531902c Fixed decoding of MASK register 2017-06-29 21:07:08 +02:00
flobernd 1fe1894362 Minor bugfixes 2017-06-29 20:54:36 +02:00
flobernd aca1ad1414 Minor bugfixes 2017-06-29 20:52:35 +02:00
flobernd d7c81e5104 Fixed operand-size of some special MVEX instructions 2017-06-29 20:40:48 +02:00
flobernd 2ee8332529 Fixed operand-action for MVEX-instructions with `READWRITE` operands 2017-06-29 20:06:44 +02:00
flobernd 8ef597970d Minor bugfixes 
- Fixed operand-action for MVEX instructions with mask-register
- Fixed decoding of MVEX instructions without swizzle/broadcast/convert functionality
 2017-06-29 19:44:01 +02:00
flobernd 65fe4a4e6c Improved instruction decoding 
- Decoding of EVEX/MVEX instructions without a NDS/NDD-operand encoded in `.vvvv` and without a VSIB-operand will now fail, if `.v'` is != 1b
- Added information about XACQUIRE, XRELEASE and BOUND prefixes to the instruction definitions
- Fixed immediate-decoding of the `vpermil2pd` / `vpermil2ps` instruction
 2017-06-29 18:09:42 +02:00
flobernd 778b47c02f Minor bugfixes 
- Fixed segment register for implicit memory-operands
- Fixed decoding of `MOV CR, GPR`, `MOV GPR, CR`, `MOV DR, GPR` and `MOV GPR, DR`
 2017-06-28 22:18:12 +02:00
flobernd 05817fa8e7 Fixed register decoding for XOP and VEX instructions (again) 2017-06-28 20:50:32 +02:00
flobernd 808ccac372 Fixed register decoding for XOP and VEX instructions 2017-06-28 20:46:32 +02:00
flobernd b118637dae Cleaned up register-decoding code 2017-06-28 19:50:33 +02:00
flobernd 55400e9206 Improved decoding of XOP/VEX/EVEX/MVEX instructions 
Decoding of XOP/VEX/EVEX/MVEX instructions without a NDS register encoded in .vvvv will now fail, if the .vvvv value is != 1111b
 2017-06-27 04:14:17 +02:00
flobernd e7a7be70e9 Performance optimizations 2017-06-27 03:32:42 +02:00
flobernd 920d62d699 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 03:20:26 +02:00
flobernd a1551af657 Fixed decoding of operands with VSIB index-register 2017-06-26 03:12:18 +02:00
flobernd 99de0f3152 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:54:49 +02:00
flobernd e15279ed1f Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:02:00 +02:00
flobernd 652b5afadb Fixed operand-action for EVEX/MVEX instructions with write-mask 2017-06-25 23:49:19 +02:00
flobernd 3b45ae2f1d Minor bugfixes 2017-06-25 23:29:42 +02:00
flobernd 83699fe9d0 Minor bugfixes 2017-06-25 23:24:43 +02:00
flobernd 96a7197647 Fixed segment-register priority in 64-bit mode 2017-06-24 04:35:48 +02:00
flobernd 3a346b5e9d Fixed segment-register for XOP/VEX/EVEX/MVEX instructions 2017-06-24 03:29:35 +02:00
flobernd 7d77e0747f Minor improvements to the instruction-decoder 
- Set mask-mode to "merge" for all MVEX instructions
- Set operand-action of EVEX dest-operands to RCW, if a merge write-mask is specified
 2017-06-24 03:20:45 +02:00
flobernd e04adf2b8d Fixed semantic decoding of EIP/RIP-relative displacements 2017-06-24 03:02:03 +02:00
flobernd 83ea3bc2c8 Minor bugfixes 2017-06-24 02:48:14 +02:00
flobernd 39bdaeeeb9 Some changes to the instruction-formatter 2017-06-24 02:16:16 +02:00
flobernd 0957a57ab4 Fixed vector-length for EVEX instructions with fixed vector-length 2017-06-24 00:01:21 +02:00
flobernd b3d508850f Added information for VEX/EVEX/MVEX instructions with static broadcast-factor 2017-06-23 20:47:34 +02:00
flobernd cd3bf5586b Changed default element-count from 0 to 1 2017-06-23 04:26:21 +02:00
flobernd c8c3d29ba4 Added support for MVEX instructions with static broadcast factor 2017-06-23 03:35:12 +02:00
flobernd 2297c763cf Added compressed disp8 calculation for MVEX instructions with element-granularity 2017-06-23 01:40:19 +02:00
flobernd d8f3843f57 Added compressed disp8 calculation for MVEX instructions without swizzle/broadcast/convert functionality 2017-06-23 01:15:42 +02:00
flobernd 6c370d29c9 Added support for some MVEX special-cases 2017-06-22 22:10:18 +02:00
flobernd 4d3a71369b Removed EVEX tuple-type and element-size from the public info-struct 2017-06-22 19:54:35 +02:00
flobernd b9c43d83a7 Added compressed disp8 calculation for MVEX instructions 2017-06-22 19:39:43 +02:00
flobernd 76f0bcf00d Improved semantic decoding of MVEX instructions 2017-06-22 19:14:27 +02:00
flobernd 2a0525925f Added decoding of MVEX swizzle/conversion and rounding-control values 2017-06-22 02:42:16 +02:00
flobernd 5bd81b7f1c Fixed sign-extension of displacement values 2017-06-22 01:38:41 +02:00
flobernd 433ca68926 Fixed formatting of sign-extended immediate operands 2017-06-21 18:30:11 +02:00
flobernd bd38d86986 Updated CMake file and Zydis features 2017-06-21 18:25:53 +02:00
flobernd dc62509b9b Ignore REX-prefix, if it is not the last prefix before the opcode 2017-06-21 04:04:58 +02:00
flobernd 9628fb8367 Fixed order of segment-registers 2017-06-21 03:03:13 +02:00
flobernd 6ff954f585 Fixed MVEX.SSS error-condition 2017-06-20 22:56:25 +02:00
flobernd d475231a63 Fixed decoding of implicit "1" immediate (ROL, ROR, RCL, ...) 2017-06-20 22:44:37 +02:00
flobernd 5112e61fd8 Fixed element-type for AGEN operands 2017-06-20 22:02:40 +02:00
flobernd 52e1b59702 Improved EVEX and MVEX encoding 
- Added some MASK related error-conditions
- Added functionality and mask-policy attributes to the MVEX instruction-definition struct
- Added MVEX specific error-condition
 2017-06-20 21:23:06 +02:00
flobernd 95b685a29d Minor bugfixes 
- Fixed some VEX/EVEX/MVEX-prefix error conditions
- MASK register size is now 64-bit for EVEX- and 16-bit for MVEX-instructions
 2017-06-20 17:48:55 +02:00
flobernd 17358016d9 Allowed custom operand-sizes for register operands 2017-06-20 03:16:17 +02:00
flobernd ee97ae753c Fixed some EVEX tuple-types 2017-06-19 20:46:42 +02:00
flobernd 4bceac86c9 Various bugfixes 
- Fixed operand-size and element-count of AGEN operands
- Fixed decoding of 8-bit modrm.rm register-operands
- Fixed vector-length for EVEX instructions with rounding-semantics
 2017-06-19 20:19:21 +02:00
flobernd 2d2e1acf27 Added T1_4X tuple-type 2017-06-18 22:02:59 +02:00
flobernd f20dc484cd Fixed priority of mandatory-prefixes 2017-06-17 21:01:57 +02:00
flobernd 58b15163f2 Improved decoding of PTR and AGEN operands 2017-06-17 02:50:08 +02:00
flobernd 6794495f63 Various bugfixes 
- Fixed decoding of XOP/VEX instructions with 256-bit vector length
- Fixed decoding of instructions with hardcoded displacement values (e.g. MOFFS)
- Fixed decoding of instructions that make use of the "ANY" mandatory-prefix filter
 2017-06-17 00:59:42 +02:00
flobernd 1d023c2997 Implemented decoding of PTR and AGEN operands 2017-06-17 00:20:44 +02:00
flobernd ad35e81eee Added semantic element-information for operands 2017-06-16 23:19:57 +02:00
flobernd 44792f2338 Added semantic decoding of implicit memory operands 2017-06-16 16:27:37 +02:00
flobernd 1db4db9ec2 Added semantic decoding of implicit register operands 2017-06-16 03:25:39 +02:00
flobernd 6caa68b674 Reimplemented decoding of 3DNOW instructions and improved EVEX decoding 2017-06-13 22:04:29 +02:00
flobernd 702f6b8d53 Reimplemented a basic version of semantic operand-decoding 2017-06-13 20:17:20 +02:00
flobernd 26d39cc7f0 Fixed XOP decoding 2017-06-12 21:07:43 +02:00
flobernd 8740b1e50f Major changes to the instruction decoder 
- Decoupled semantic operand decoding (optional) from physical instruction decoding
- Several optimizations of the internal structures
- Further preparations for MVEX-support
 2017-06-12 19:16:01 +02:00
Joel Höner d3192a8be7 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-05-05 19:26:13 +02:00
Joel Höner de666d7a4a Improved handling of unreachable code 2017-05-05 19:26:03 +02:00
flobernd baa1bc243a Fixed decoding of VEX/EVEX instructions with high-register-specifiers 2017-04-25 17:46:02 +02:00
Joel Höner 40d6c39dbe Renamed disassembler mode constants 
ZYDIS_DISASSEMBLER_MODE_* -> ZYDIS_OPERATING_MODE_*
 2017-04-12 21:12:18 +02:00
flobernd 71a6d786d7 Minor bugfixes and cosmetical changes 2017-04-12 21:00:46 +02:00
Joel Höner ebf71d632f Moved `internal` sub-struct from info to context 
Also, fixed examples and tools.
 2017-04-11 03:18:08 +02:00
Joel Höner 71a551ef1a Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-04-11 02:20:02 +02:00
Joel Höner c9606c389d Removed obsolete public decoder struct 2017-04-11 02:19:53 +02:00
flobernd 8dd599555f Further improvements on #13 2017-04-09 23:11:16 +02:00
Joel Höner 3b47ed4a9a Fixed inaccurate relative operands on decoding 
Resolves #13
 2017-04-09 20:55:49 +02:00
Joel Höner fda4f15c6d Many encoder bug-fixes, movabs support 2017-01-23 21:52:26 +01:00
Joel Höner 616cd00ec8 Encoder support for rIP relative addressing 2017-01-23 19:21:15 +01:00
Joel Höner 0862398940 Various encoder bug-fixes 2017-01-23 18:31:50 +01:00
Joel Höner 781b9641c4 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-01-23 01:37:45 +01:00
flobernd 8157b9fa42 Temporary change to expose the semantic operand-type 2017-01-23 01:17:15 +01:00
Joel Höner 4fe029a34e Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-01-22 22:12:24 +01:00
Joel Höner eb64a23231 Added encoding of opcode bits into ModRM 2017-01-22 22:12:06 +01:00
flobernd deff3b8e55 Fixed register encoding 2017-01-22 21:44:42 +01:00
Joel Höner 1faec66a66 Fixed mandatory prefixes, added prefix compatibility checks 2017-01-22 19:02:07 +01:00
Joel Höner cb98db80ea Minor encoder cleanup 2017-01-22 17:38:14 +01:00
Joel Höner 587187af89 Implemented address size prefix encoding, bugfixes 2017-01-22 15:46:20 +01:00
Joel Höner b3c8d44bda Implemented segment prefix encoding, refactoring 
- Moved memory operand encoding into dedicated function
 2017-01-21 23:53:50 +01:00
Joel Höner 87e80346f4 Fixed tools 2017-01-21 18:15:37 +01:00
Joel Höner 03e26408fe Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-01-21 01:48:35 +01:00
Joel Höner 0a50bb9daa Implemented encoding for XOP, VEX and EVEX 2017-01-20 21:18:13 +01:00
Joel Höner 46077709f8 Completed SIB encoding 2017-01-20 00:54:48 +01:00
flobernd 98d34d0c62 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-01-20 00:03:28 +01:00
flobernd dc70ee7eb2 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-01-20 00:02:21 +01:00
flobernd 4b54158aa2 Minor bugfixes 2017-01-20 00:01:56 +01:00
Joel Höner c0f53a3a69 More encoder progress, minor refactoring 
- Added encoding support for more X86 features (IMMs, SIB, ..)
- Added ZYDIS_ARRAY_SIZE macro
- Moved ZYDIS_MAX_INSTRUCTION_LENGTH (Decoder.h -> InstructionInfo.h)
- Renamed ZydisInstructionEncoder -> ZydisEncoderContext
- Various bug-fixes
 2017-01-19 17:37:05 +01:00
Joel Höner 14848083ae More encoder progress 2017-01-17 20:53:34 +01:00
flobernd 5ead1d9345 Minor refactorings 
- The instruction pointer is now directly passed to the ZydisDecoderDecodeInstruction function
- Removed the user-data pointer in the ZydisOperandInfo struct
 2017-01-12 20:14:12 +01:00
Joel Höner 689708fbd3 Refactored docstrings to use uppercase abbreviations 2017-01-12 19:37:57 +01:00
Joel Höner a9514fbfea Minor documentation and style fixes 2017-01-12 18:54:16 +01:00
Joel Höner 0793090388 Implemented basic prefix encoding 2017-01-12 18:53:28 +01:00
Joel Höner 3d2365b6ed Added encoder stub, made decoder input const 2017-01-12 15:12:09 +01:00
flobernd 5af25eee4b Fixed a bug in ZYDIS_CHECK that caused functions to run more than once on certain conditions 2017-01-11 17:29:26 +01:00
flobernd c0528d5cb0 Exposed ZYDIS_MAX_INSTRUCTION_LENGTH constant 2017-01-11 11:24:10 +01:00
flobernd 4165c3b9b2 Removed Input-struct. The input buffer is now directly passed to the ZydisDecodeInstruction function. 2017-01-11 11:20:24 +01:00
Joel Höner b291c8a760 Use size_t instead of uint64_t for memory input 2017-01-07 00:29:16 +01:00