mirror of https://github.com/x64dbg/zydis
`REX.R` and `REX.B` is ignored for non-GPR/VR/CR/DR registers
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@ -920,9 +920,21 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context,
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{
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ZYDIS_ASSERT(instruction->raw.modrm.isDecoded);
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uint8_t value = instruction->raw.modrm.reg;
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if (registerClass != ZYDIS_REGCLASS_MASK)
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switch (registerClass)
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{
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value |= (context->cache.R << 3);
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case ZYDIS_REGCLASS_GPR8:
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case ZYDIS_REGCLASS_GPR16:
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case ZYDIS_REGCLASS_GPR32:
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case ZYDIS_REGCLASS_GPR64:
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case ZYDIS_REGCLASS_XMM:
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case ZYDIS_REGCLASS_YMM:
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case ZYDIS_REGCLASS_ZMM:
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case ZYDIS_REGCLASS_CONTROL:
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case ZYDIS_REGCLASS_DEBUG:
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value |= (context->cache.R << 3);
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break;
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default:
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break;
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}
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// R' only exists for EVEX and MVEX. No encoding check needed
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switch (registerClass)
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@ -954,9 +966,21 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context,
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{
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ZYDIS_ASSERT(instruction->raw.modrm.isDecoded);
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uint8_t value = instruction->raw.modrm.rm;
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if (registerClass != ZYDIS_REGCLASS_MASK)
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switch (registerClass)
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{
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value |= (context->cache.B << 3);
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case ZYDIS_REGCLASS_GPR8:
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case ZYDIS_REGCLASS_GPR16:
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case ZYDIS_REGCLASS_GPR32:
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case ZYDIS_REGCLASS_GPR64:
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case ZYDIS_REGCLASS_XMM:
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case ZYDIS_REGCLASS_YMM:
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case ZYDIS_REGCLASS_ZMM:
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case ZYDIS_REGCLASS_CONTROL:
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case ZYDIS_REGCLASS_DEBUG:
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value |= (context->cache.B << 3);
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break;
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default:
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break;
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}
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// We have to check the instruction-encoding, because the extension by X is only valid
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// for EVEX and MVEX instructions
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