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zydis
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  • e15279ed1f Fixed operand-action for EVEX/MVEX instructions with write-mask (again) flobernd 2017-06-26 00:02:00 +0200
  • 0c38e08306 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop flobernd 2017-06-25 23:50:13 +0200
  • 652b5afadb Fixed operand-action for EVEX/MVEX instructions with write-mask flobernd 2017-06-25 23:49:19 +0200
  • 3b45ae2f1d Minor bugfixes flobernd 2017-06-25 23:29:42 +0200
  • b442fa55b4 Fixed tools Joel Höner 2017-06-25 23:28:15 +0200
  • 83699fe9d0 Minor bugfixes flobernd 2017-06-25 23:24:43 +0200
  • 96a7197647 Fixed segment-register priority in 64-bit mode flobernd 2017-06-24 04:35:48 +0200
  • 3a346b5e9d Fixed segment-register for XOP/VEX/EVEX/MVEX instructions flobernd 2017-06-24 03:29:35 +0200
  • 7d77e0747f Minor improvements to the instruction-decoder flobernd 2017-06-24 03:20:45 +0200
  • e04adf2b8d Fixed semantic decoding of EIP/RIP-relative displacements flobernd 2017-06-24 03:02:03 +0200
  • 83ea3bc2c8 Minor bugfixes flobernd 2017-06-24 02:48:14 +0200
  • 39bdaeeeb9 Some changes to the instruction-formatter flobernd 2017-06-24 02:16:16 +0200
  • f0d1ef9725 Added some missing instructions flobernd 2017-06-24 02:11:32 +0200
  • 0957a57ab4 Fixed vector-length for EVEX instructions with fixed vector-length flobernd 2017-06-24 00:01:21 +0200
  • b3d508850f Added information for VEX/EVEX/MVEX instructions with static broadcast-factor flobernd 2017-06-23 20:47:34 +0200
  • cd3bf5586b Changed default element-count from 0 to 1 flobernd 2017-06-23 04:26:21 +0200
  • c8c3d29ba4 Added support for MVEX instructions with static broadcast factor flobernd 2017-06-23 03:35:12 +0200
  • 2297c763cf Added compressed disp8 calculation for MVEX instructions with element-granularity flobernd 2017-06-23 01:40:19 +0200
  • d8f3843f57 Added compressed disp8 calculation for MVEX instructions without swizzle/broadcast/convert functionality flobernd 2017-06-23 01:15:42 +0200
  • 6c370d29c9 Added support for some MVEX special-cases flobernd 2017-06-22 22:10:18 +0200
  • 4d3a71369b Removed EVEX tuple-type and element-size from the public info-struct flobernd 2017-06-22 19:54:35 +0200
  • b9c43d83a7 Added compressed disp8 calculation for MVEX instructions flobernd 2017-06-22 19:39:43 +0200
  • 76f0bcf00d Improved semantic decoding of MVEX instructions flobernd 2017-06-22 19:14:27 +0200
  • 2a0525925f Added decoding of MVEX swizzle/conversion and rounding-control values flobernd 2017-06-22 02:42:16 +0200
  • 15f89dc4ea Fixed a bitfield-size error flobernd 2017-06-22 01:40:20 +0200
  • 5bd81b7f1c Fixed sign-extension of displacement values flobernd 2017-06-22 01:38:41 +0200
  • 433ca68926 Fixed formatting of sign-extended immediate operands flobernd 2017-06-21 18:30:11 +0200
  • bd38d86986 Updated CMake file and Zydis features flobernd 2017-06-21 18:25:53 +0200
  • dc62509b9b Ignore REX-prefix, if it is not the last prefix before the opcode flobernd 2017-06-21 04:04:58 +0200
  • 9628fb8367 Fixed order of segment-registers flobernd 2017-06-21 03:03:13 +0200
  • 6ff954f585 Fixed MVEX.SSS error-condition flobernd 2017-06-20 22:56:25 +0200
  • d475231a63 Fixed decoding of implicit "1" immediate (ROL, ROR, RCL, ...) flobernd 2017-06-20 22:44:37 +0200
  • 5112e61fd8 Fixed element-type for AGEN operands flobernd 2017-06-20 22:02:40 +0200
  • 52e1b59702 Improved EVEX and MVEX encoding flobernd 2017-06-20 21:23:06 +0200
  • 95b685a29d Minor bugfixes flobernd 2017-06-20 17:48:55 +0200
  • 17358016d9 Allowed custom operand-sizes for register operands flobernd 2017-06-20 03:16:17 +0200
  • 4487d1b252 Fixed some operand-size related filter-tables flobernd 2017-06-20 01:33:07 +0200
  • 0902068007 Fixed more EVEX tuple-types flobernd 2017-06-19 21:06:33 +0200
  • ee97ae753c Fixed some EVEX tuple-types flobernd 2017-06-19 20:46:42 +0200
  • 4bceac86c9 Various bugfixes flobernd 2017-06-19 20:19:21 +0200
  • 2d2e1acf27 Added T1_4X tuple-type flobernd 2017-06-18 22:02:59 +0200
  • f20dc484cd Fixed priority of mandatory-prefixes flobernd 2017-06-17 21:01:57 +0200
  • 58b15163f2 Improved decoding of PTR and AGEN operands flobernd 2017-06-17 02:50:08 +0200
  • 6794495f63 Various bugfixes flobernd 2017-06-17 00:59:42 +0200
  • 1d023c2997 Implemented decoding of PTR and AGEN operands flobernd 2017-06-17 00:20:44 +0200
  • 28a8178559 Fixed compatibility problem flobernd 2017-06-16 23:38:06 +0200
  • ad35e81eee Added semantic element-information for operands flobernd 2017-06-16 23:19:57 +0200
  • 44792f2338 Added semantic decoding of implicit memory operands flobernd 2017-06-16 16:27:37 +0200
  • 1db4db9ec2 Added semantic decoding of implicit register operands flobernd 2017-06-16 03:25:39 +0200
  • 6caa68b674 Reimplemented decoding of 3DNOW instructions and improved EVEX decoding flobernd 2017-06-13 22:04:29 +0200
  • 702f6b8d53 Reimplemented a basic version of semantic operand-decoding flobernd 2017-06-13 20:17:20 +0200
  • 26d39cc7f0 Fixed XOP decoding flobernd 2017-06-12 21:07:43 +0200
  • 8740b1e50f Major changes to the instruction decoder flobernd 2017-06-12 19:16:01 +0200
  • e5e5899f72 Preparations for MVEX-support and decoupling of operand-decoding flobernd 2017-05-08 18:18:08 +0200
  • d3192a8be7 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop Joel Höner 2017-05-05 19:26:13 +0200
  • de666d7a4a Improved handling of unreachable code Joel Höner 2017-05-05 19:26:03 +0200
  • baa1bc243a Fixed decoding of VEX/EVEX instructions with high-register-specifiers flobernd 2017-04-25 17:46:02 +0200
  • 40d6c39dbe Renamed disassembler mode constants Joel Höner 2017-04-12 21:12:18 +0200
  • 71a6d786d7 Minor bugfixes and cosmetical changes flobernd 2017-04-12 21:00:46 +0200
  • ebf71d632f Moved `internal` sub-struct from info to context Joel Höner 2017-04-11 03:18:08 +0200
  • 71a551ef1a Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop Joel Höner 2017-04-11 02:20:02 +0200
  • c9606c389d Removed obsolete public decoder struct Joel Höner 2017-04-11 02:19:53 +0200
  • 8dd599555f Further improvements on #13 flobernd 2017-04-09 23:11:16 +0200
  • 839729bfb2 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop flobernd 2017-04-09 22:57:30 +0200
  • b4f2d3bc62 CMake bugfix and cosmetical changes to the README file flobernd 2017-04-09 22:54:53 +0200
  • e825b6ed78 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop Joel Höner 2017-04-09 20:56:08 +0200
  • 3b47ed4a9a Fixed inaccurate relative operands on decoding Joel Höner 2017-04-09 20:55:49 +0200
  • 70cb75eec7 Merge pull request #12 from mrexodia/patch-1 Joel Höner 2017-04-08 21:03:32 +0200
  • ae5a900591 changes AccessMode to Action in frmMain Duncan Ogilvie 2017-04-08 20:33:58 +0200
  • 0376376b83 Temp. disabled encoder, updated CMake defaults Joel Höner 2017-04-08 19:36:16 +0200
  • fda4f15c6d Many encoder bug-fixes, movabs support develop Joel Höner 2017-01-23 21:52:26 +0100
  • 616cd00ec8 Encoder support for rIP relative addressing Joel Höner 2017-01-23 19:21:15 +0100
  • 0862398940 Various encoder bug-fixes Joel Höner 2017-01-23 18:31:50 +0100
  • 781b9641c4 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop Joel Höner 2017-01-23 01:37:45 +0100
  • 8157b9fa42 Temporary change to expose the semantic operand-type flobernd 2017-01-23 01:17:15 +0100
  • 4fe029a34e Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop Joel Höner 2017-01-22 22:12:24 +0100
  • eb64a23231 Added encoding of opcode bits into ModRM Joel Höner 2017-01-22 22:12:06 +0100
  • deff3b8e55 Fixed register encoding flobernd 2017-01-22 21:44:42 +0100
  • 1faec66a66 Fixed mandatory prefixes, added prefix compatibility checks Joel Höner 2017-01-22 19:02:07 +0100
  • cb98db80ea Minor encoder cleanup Joel Höner 2017-01-22 17:38:14 +0100
  • 587187af89 Implemented address size prefix encoding, bugfixes Joel Höner 2017-01-22 15:46:20 +0100
  • b3c8d44bda Implemented segment prefix encoding, refactoring Joel Höner 2017-01-21 23:53:50 +0100
  • 87e80346f4 Fixed tools Joel Höner 2017-01-21 18:15:37 +0100
  • 03e26408fe Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop Joel Höner 2017-01-21 01:48:35 +0100
  • 0a50bb9daa Implemented encoding for XOP, VEX and EVEX Joel Höner 2017-01-20 21:18:13 +0100
  • 46077709f8 Completed SIB encoding Joel Höner 2017-01-20 00:54:48 +0100
  • 98d34d0c62 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop flobernd 2017-01-20 00:03:28 +0100
  • dc70ee7eb2 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop flobernd 2017-01-20 00:02:21 +0100
  • 4b54158aa2 Minor bugfixes flobernd 2017-01-20 00:01:56 +0100
  • c0f53a3a69 More encoder progress, minor refactoring Joel Höner 2017-01-19 17:37:05 +0100
  • 14848083ae More encoder progress Joel Höner 2017-01-17 20:53:34 +0100
  • 5ead1d9345 Minor refactorings flobernd 2017-01-12 20:14:12 +0100
  • 689708fbd3 Refactored docstrings to use uppercase abbreviations Joel Höner 2017-01-12 19:37:57 +0100
  • a9514fbfea Minor documentation and style fixes Joel Höner 2017-01-12 18:54:16 +0100
  • 0793090388 Implemented basic prefix encoding Joel Höner 2017-01-12 18:53:28 +0100
  • 3d2365b6ed Added encoder stub, made decoder input const Joel Höner 2017-01-12 15:12:09 +0100
  • 67231ccdff Increased read buffer size in tools Joel Höner 2017-01-12 10:29:42 +0100
  • 3b56c867fc Updated mask-policy definitions for EVEX instructions flobernd 2017-01-11 22:11:30 +0100
  • 794a769800 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop flobernd 2017-01-11 17:29:36 +0100
  • 5af25eee4b Fixed a bug in ZYDIS_CHECK that caused functions to run more than once on certain conditions flobernd 2017-01-11 17:29:26 +0100