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zydis
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Commit Graph

172 Commits

Author SHA1 Message Date
flobernd 5d6c58ad1c Fixed `ZydisISAExt` enum 2017-09-10 20:43:01 +02:00
flobernd fec4116ad6 Minor refactorings and bugfixes 
- Added the `ZYDIS_ATTRIB_HAS_MVEX` attribute
- Updated attribute macro values
- Changed size of `ZydisDecodeGranularity` from 32-bit to 8-bit
 2017-09-09 14:16:54 +02:00
flobernd 5914abc0be Tables fixes and more meta-info 
- Added exception-class meta-info
- Added CMake option for shared-libraries
- Fixed some instruction-definitions
- Updated VersionInfo.rc
 2017-09-06 17:05:05 +02:00
flobernd fafa93d40b Internal refactorings and new meta-info 
- Imported meta-info from Intel XED
- Added instruction-category meta-info to the `ZydisDecodedInstruction` struct
- Added isa-set meta-info to the `ZydisDecodedInstruction` struct
- Added isa-extension meta-info to the `ZydisDecodedInstruction` struct
 2017-09-05 17:35:23 +02:00
flobernd 14d87fda8b Fixed wrong return value of `ZydisFormatterSetHook` 2017-08-23 20:40:57 +02:00
flobernd f89398877d Merge branch 'master' into develop 2017-08-15 14:33:07 +02:00
flobernd 74484aec2e Removed trailing whitespace after mnemonic for instructions without visible operands 2017-08-14 17:10:24 +02:00
Joel Höner c0fd657f15 Merged internal encoder AVX/REX structs 
- It was pretty redundant before
  - Required unnecessary routing logic
  - Minor decrease of required stack memory
- Added `ZydisEmitMVEX` and generally more MVEX support
 2017-08-03 02:04:39 +02:00
Joel Höner 9437e89006 More encoder progress 2017-08-03 01:25:25 +02:00
Joel Höner 87394ef4da Added basic support for Windows kernel drivers 
- Manual typedefs for fixed width int types
- Custom `vsnprintf` function
- Disable ZYDIS_ASSERT and ZYDIS_UNREACHABLE
 2017-07-28 22:25:20 +02:00
Joel Höner 5ac595eb72 Major rework of encoder context design 
- Split into various smaller structs
- Only hand functions parts they actually need
 2017-07-28 03:13:30 +02:00
Joel Höner 9152714865 Fixed encoder IMM size derivation 2017-07-28 02:26:52 +02:00
Joel Höner 4140db6c1f Encoder progress, ZYDIS_UNREACHABLE for MSVC 2017-07-28 00:37:52 +02:00
flobernd 03ef968413 `REX.R` and `REX.B` is ignored for non-GPR/VR/CR/DR registers 2017-07-26 18:17:59 +02:00
flobernd cde97dca36 Fixed a bug that caused the formatter to falsely print a `{sae}` decorator in some cases 2017-07-25 14:58:17 +02:00
flobernd 7434bea839 Fixed some `EVEX` instruction-definitions 
- A bug in the table generator caused inverted conditions regarding zero-mask support for some `EVEX` instructions
 2017-07-25 14:30:32 +02:00
flobernd 341f3866c3 Various changes to the instruction-definitions and decoder/encoder-tables 2017-07-19 18:43:59 +02:00
flobernd e76c3d64c3 Added missing instructions to the encoder-table 2017-07-18 22:38:56 +02:00
flobernd 54d3836256 Minor improvements to the instruction-formatter 2017-07-15 03:39:48 +02:00
flobernd 9e15ecc5f1 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-07-14 22:56:06 +02:00
flobernd 53e89b0800 Replaced `EVEX.z` filter by `acceptsZeroMask` attribute 2017-07-14 22:54:22 +02:00
Joel Höner 58fffa4e71 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-07-12 23:57:25 +02:00
Joel Höner ebd1e18d0f More work in the operand encoding derivation logic 2017-07-12 23:57:20 +02:00
flobernd 59fa404919 Added detailed information about accessed CPU-flags 2017-07-12 17:48:02 +02:00
flobernd 13a2858210 Added hidden R/E/FLAGS register operands 2017-07-12 15:44:47 +02:00
flobernd 682c647eb6 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-07-11 22:22:33 +02:00
flobernd bb1708daaf Preparations for the CPU-flag info feature 2017-07-11 18:51:54 +02:00
Joel Höner 743048852c More encoder progress 2017-07-10 23:43:52 +02:00
Joel Höner 3498a33944 More clean-up in the encoder 2017-07-10 14:34:25 +02:00
flobernd 8fa80f0b86 Minor bugfixes and improvement of the encoder-table 
- Fixed scale-factor of memory operands, if SIB byte is used
- Fixed operand-encoding missing for some operands
- Added operand-size and address-size filters to the encoder-table
 2017-07-09 18:06:43 +02:00
flobernd 5c07598a2d Improved encoder-table 2017-07-06 21:49:38 +02:00
Joel Höner 6bd79283e0 Fixed encoder header 2017-07-06 13:12:43 +02:00
Joel Höner 610d08960b Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 
# Conflicts:
#	CMakeLists.txt
 2017-07-06 08:17:38 +02:00
Joel Höner 41776bac29 Updated encoder to a lot of previous refactorings 2017-07-06 08:07:22 +02:00
flobernd df2dbd9109 Refactorings 
- Renamed Types.h to CommonTypes.h
- Splitted DecoderTypes.h into SharedTypes.h and DecoderTypes.h
- Splitted InstructionTable.h into SharedData.h and DecoderData.h
- Implemented `ZydisGetEncodableInstructions` in EncoderData.h
- Some internal changes to the data-tables
 2017-07-06 00:34:36 +02:00
flobernd f8f928a4a8 Added number of decoded instructions to the performance-test tool output 2017-07-05 16:28:16 +02:00
flobernd 428da82416 Added `ZYDIS_ATTRIB_IS_PRIVILEGED` 2017-07-05 13:47:54 +02:00
flobernd 34a0572948 Refactorings 2017-07-05 13:33:59 +02:00
flobernd 8a626388ae Improved formatting of decorators 2017-07-04 19:02:11 +02:00
flobernd af0c6c8cac Removed EVEX/MVEX compressed 8-bit displacement scale-factor from the public interface (for now) 2017-07-04 16:26:03 +02:00
flobernd b9cf56af4d Refactorings 2017-07-04 16:10:21 +02:00
flobernd bbf8b1193b Added performance test 2017-07-03 21:10:04 +02:00
flobernd 87c9155207 Refactorings 2017-07-03 17:36:03 +02:00
flobernd 6ce34bd141 Added error-condition for illegal LOCK-prefixes 2017-07-03 17:02:32 +02:00
Joel Höner 7ba6ea0596 Moved private headers to `src` directory 2017-07-03 04:16:38 +02:00
flobernd 38c67d2a85 Refactorings 2017-07-03 03:14:01 +02:00
flobernd ad8e5ce6a9 Minor refactorings 2017-07-01 01:10:03 +02:00
flobernd 392c36c85f Fixed decoding of MASK register (again) 2017-06-29 21:12:22 +02:00
flobernd c2a531902c Fixed decoding of MASK register 2017-06-29 21:07:08 +02:00
flobernd 1fe1894362 Minor bugfixes 2017-06-29 20:54:36 +02:00