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zydis
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347 Commits 3 Branches 1 Tag 8.5 MiB
Commit Graph

117 Commits

Author SHA1 Message Date
flobernd 01b8267d47 Minor refactorings 
- Adjusted datatype of some enums
- Renamed some things
  - `ZydisDecodedInstruction.flags` -> `ZydisDecodedInstruction.accessedFlags`
  - `ZydisDecodedInstruction.meta.roundingMode` -> `ZydisDecodedInstruction.meta.rounding.mode`
  - `ZydisDecodedInstruction.meta.swizzleMode` -> `ZydisDecodedInstruction.meta.swizzle.mode`
  - `ZydisDecodedInstruction.meta.conversionMode` -> `ZydisDecodedInstruction.meta.conversion.mode`
  - `ZydisGetCPUFlagsByAction` -> `ZydisGetAccessedFlagsByAction`
 2017-09-10 21:43:52 +02:00
flobernd fec4116ad6 Minor refactorings and bugfixes 
- Added the `ZYDIS_ATTRIB_HAS_MVEX` attribute
- Updated attribute macro values
- Changed size of `ZydisDecodeGranularity` from 32-bit to 8-bit
 2017-09-09 14:16:54 +02:00
flobernd 5914abc0be Tables fixes and more meta-info 
- Added exception-class meta-info
- Added CMake option for shared-libraries
- Fixed some instruction-definitions
- Updated VersionInfo.rc
 2017-09-06 17:05:05 +02:00
flobernd fafa93d40b Internal refactorings and new meta-info 
- Imported meta-info from Intel XED
- Added instruction-category meta-info to the `ZydisDecodedInstruction` struct
- Added isa-set meta-info to the `ZydisDecodedInstruction` struct
- Added isa-extension meta-info to the `ZydisDecodedInstruction` struct
 2017-09-05 17:35:23 +02:00
flobernd f89398877d Merge branch 'master' into develop 2017-08-15 14:33:07 +02:00
Joel Höner 4140db6c1f Encoder progress, ZYDIS_UNREACHABLE for MSVC 2017-07-28 00:37:52 +02:00
flobernd 03ef968413 `REX.R` and `REX.B` is ignored for non-GPR/VR/CR/DR registers 2017-07-26 18:17:59 +02:00
flobernd 341f3866c3 Various changes to the instruction-definitions and decoder/encoder-tables 2017-07-19 18:43:59 +02:00
flobernd 53e89b0800 Replaced `EVEX.z` filter by `acceptsZeroMask` attribute 2017-07-14 22:54:22 +02:00
flobernd 59fa404919 Added detailed information about accessed CPU-flags 2017-07-12 17:48:02 +02:00
flobernd 8fa80f0b86 Minor bugfixes and improvement of the encoder-table 
- Fixed scale-factor of memory operands, if SIB byte is used
- Fixed operand-encoding missing for some operands
- Added operand-size and address-size filters to the encoder-table
 2017-07-09 18:06:43 +02:00
flobernd 5c07598a2d Improved encoder-table 2017-07-06 21:49:38 +02:00
flobernd df2dbd9109 Refactorings 
- Renamed Types.h to CommonTypes.h
- Splitted DecoderTypes.h into SharedTypes.h and DecoderTypes.h
- Splitted InstructionTable.h into SharedData.h and DecoderData.h
- Implemented `ZydisGetEncodableInstructions` in EncoderData.h
- Some internal changes to the data-tables
 2017-07-06 00:34:36 +02:00
flobernd f8f928a4a8 Added number of decoded instructions to the performance-test tool output 2017-07-05 16:28:16 +02:00
flobernd 428da82416 Added `ZYDIS_ATTRIB_IS_PRIVILEGED` 2017-07-05 13:47:54 +02:00
flobernd 34a0572948 Refactorings 2017-07-05 13:33:59 +02:00
flobernd 8a626388ae Improved formatting of decorators 2017-07-04 19:02:11 +02:00
flobernd af0c6c8cac Removed EVEX/MVEX compressed 8-bit displacement scale-factor from the public interface (for now) 2017-07-04 16:26:03 +02:00
flobernd b9cf56af4d Refactorings 2017-07-04 16:10:21 +02:00
flobernd bbf8b1193b Added performance test 2017-07-03 21:10:04 +02:00
flobernd 87c9155207 Refactorings 2017-07-03 17:36:03 +02:00
flobernd 6ce34bd141 Added error-condition for illegal LOCK-prefixes 2017-07-03 17:02:32 +02:00
Joel Höner 7ba6ea0596 Moved private headers to `src` directory 2017-07-03 04:16:38 +02:00
flobernd 38c67d2a85 Refactorings 2017-07-03 03:14:01 +02:00
flobernd ad8e5ce6a9 Minor refactorings 2017-07-01 01:10:03 +02:00
flobernd 392c36c85f Fixed decoding of MASK register (again) 2017-06-29 21:12:22 +02:00
flobernd c2a531902c Fixed decoding of MASK register 2017-06-29 21:07:08 +02:00
flobernd 1fe1894362 Minor bugfixes 2017-06-29 20:54:36 +02:00
flobernd aca1ad1414 Minor bugfixes 2017-06-29 20:52:35 +02:00
flobernd d7c81e5104 Fixed operand-size of some special MVEX instructions 2017-06-29 20:40:48 +02:00
flobernd 2ee8332529 Fixed operand-action for MVEX-instructions with `READWRITE` operands 2017-06-29 20:06:44 +02:00
flobernd 8ef597970d Minor bugfixes 
- Fixed operand-action for MVEX instructions with mask-register
- Fixed decoding of MVEX instructions without swizzle/broadcast/convert functionality
 2017-06-29 19:44:01 +02:00
flobernd 65fe4a4e6c Improved instruction decoding 
- Decoding of EVEX/MVEX instructions without a NDS/NDD-operand encoded in `.vvvv` and without a VSIB-operand will now fail, if `.v'` is != 1b
- Added information about XACQUIRE, XRELEASE and BOUND prefixes to the instruction definitions
- Fixed immediate-decoding of the `vpermil2pd` / `vpermil2ps` instruction
 2017-06-29 18:09:42 +02:00
flobernd 778b47c02f Minor bugfixes 
- Fixed segment register for implicit memory-operands
- Fixed decoding of `MOV CR, GPR`, `MOV GPR, CR`, `MOV DR, GPR` and `MOV GPR, DR`
 2017-06-28 22:18:12 +02:00
flobernd 05817fa8e7 Fixed register decoding for XOP and VEX instructions (again) 2017-06-28 20:50:32 +02:00
flobernd 808ccac372 Fixed register decoding for XOP and VEX instructions 2017-06-28 20:46:32 +02:00
flobernd b118637dae Cleaned up register-decoding code 2017-06-28 19:50:33 +02:00
flobernd 55400e9206 Improved decoding of XOP/VEX/EVEX/MVEX instructions 
Decoding of XOP/VEX/EVEX/MVEX instructions without a NDS register encoded in .vvvv will now fail, if the .vvvv value is != 1111b
 2017-06-27 04:14:17 +02:00
flobernd e7a7be70e9 Performance optimizations 2017-06-27 03:32:42 +02:00
flobernd 920d62d699 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 03:20:26 +02:00
flobernd a1551af657 Fixed decoding of operands with VSIB index-register 2017-06-26 03:12:18 +02:00
flobernd 99de0f3152 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:54:49 +02:00
flobernd e15279ed1f Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:02:00 +02:00
flobernd 652b5afadb Fixed operand-action for EVEX/MVEX instructions with write-mask 2017-06-25 23:49:19 +02:00
flobernd 3b45ae2f1d Minor bugfixes 2017-06-25 23:29:42 +02:00
flobernd 83699fe9d0 Minor bugfixes 2017-06-25 23:24:43 +02:00
flobernd 96a7197647 Fixed segment-register priority in 64-bit mode 2017-06-24 04:35:48 +02:00
flobernd 3a346b5e9d Fixed segment-register for XOP/VEX/EVEX/MVEX instructions 2017-06-24 03:29:35 +02:00
flobernd 7d77e0747f Minor improvements to the instruction-decoder 
- Set mask-mode to "merge" for all MVEX instructions
- Set operand-action of EVEX dest-operands to RCW, if a merge write-mask is specified
 2017-06-24 03:20:45 +02:00
flobernd e04adf2b8d Fixed semantic decoding of EIP/RIP-relative displacements 2017-06-24 03:02:03 +02:00