DBG: add pushfq mnemonic redirect

bin/mnemdb.json

@@ -1780,6 +1780,10 @@
       "description": "-R:PUSHF", 
       "mnem": "PUSHFD"
     }, 
+    {
+      "description": "-R:PUSHF", 
+      "mnem": "PUSHFQ"
+    }, 
     {
       "description": "\nPXOR - Logical Exclusive OR:\n| Opcode*/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                       \n| 0F EF /r1 PXOR mm, mm/m64              | RM   | V/V                   | MMX               | Bitwise XOR of mm/m64 and mm.     \n| 66 0F EF /r PXOR xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Bitwise XOR of xmm2/m128 and xmm1.\n| VEX.NDS.128.66.0F.WIG EF /r VPXOR xmm1,| RVM  | V/V                   | AVX               | Bitwise XOR of xmm3/m128 and xmm2.\n| xmm2, xmm3/m128                        |      |                       |                   |                                   \n| VEX.NDS.256.66.0F.WIG EF /r VPXOR ymm1,| RVM  | V/V                   | AVX2              | Bitwise XOR of ymm3/m256 and ymm2.\n| ymm2, ymm3/m256                        |      |                       |                   |                                   \nNotes: 1. See note in Section 2.4, \u201cInstruction Exception Specification\u201d in\nthe Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual, Volume 2A\nand Section 22.25.3, \u201cException Conditions of Legacy SIMD Instructions Operating\non MMX Registers\u201d in the Intel\u00ae 64 and IA-32 Architectures Software Developer's\nManual, Volume 3A.\n\n\nInstruction Operand Encoding:\n| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4\n| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       \n| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       \n\nDescription:\nPerforms a bitwise logical exclusive-OR (XOR) operation on the source operand\n(second operand) and the destination operand (first operand) and stores the\nresult in the destination operand. Each bit of the result is 1 if the corresponding\nbits of the two operands are different; each bit is 0 if the corresponding bits\nof the operands are the same.\n\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction\nto access additional registers (XMM8-XMM15).\n\nLegacy SSE instructions: The source operand can be an MMX technology register\nor a 64-bit memory location. The destination operand is an MMX technology register.\n128-bit Legacy SSE version: The second source operand is an XMM register or\na 128-bit memory location. The first source operand and destination operands\nare XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register\nremain unchanged. VEX.128 encoded version: The second source operand is an XMM\nregister or a 128-bit memory location. The first source operand and destination\noperands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\nare zeroed. VEX.256 encoded version: The second source operand is an YMM register\nor a 256-bit memory location. The first source operand and destination operands\nare YMM registers.\n\nNote: VEX.L must be 0, otherwise instructions will #UD.\n\nOperation:\n\nPXOR (128-bit Legacy SSE version)\nDEST <- DEST XOR SRC\nDEST[VLMAX-1:128] (Unmodified)\nVPXOR (VEX.128 encoded version)\nDEST <- SRC1 XOR SRC2\nDEST[VLMAX-1:128] <- 0\nVPXOR (VEX.256 encoded version)\nDEST <- SRC1 XOR SRC2\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| PXOR:   | __m64 _mm_xor_si64 (__m64 m1, __m64       \n|         | m2)                                       \n| (V)PXOR:| __m128i _mm_xor_si128 ( __m128i a, __m128i\n|         | b)                                        \n| VPXOR:  | __m256i _mm256_xor_si256 ( __m256i a,     \n|         | __m256i b)                                \n\nFlags Affected:\nNone.\n\n\nNumeric Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Exceptions Type 4; additionally\n\n| #UD| If VEX.L = 1.\n", 
       "mnem": "PXOR"