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zydis
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314 Commits 3 Branches 1 Tag 8.5 MiB
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156 Commits

Author SHA1 Message Date
flobernd 3b45ae2f1d Minor bugfixes 2017-06-25 23:29:42 +02:00
flobernd 83699fe9d0 Minor bugfixes 2017-06-25 23:24:43 +02:00
flobernd 96a7197647 Fixed segment-register priority in 64-bit mode 2017-06-24 04:35:48 +02:00
flobernd 3a346b5e9d Fixed segment-register for XOP/VEX/EVEX/MVEX instructions 2017-06-24 03:29:35 +02:00
flobernd 7d77e0747f Minor improvements to the instruction-decoder 
- Set mask-mode to "merge" for all MVEX instructions
- Set operand-action of EVEX dest-operands to RCW, if a merge write-mask is specified
 2017-06-24 03:20:45 +02:00
flobernd e04adf2b8d Fixed semantic decoding of EIP/RIP-relative displacements 2017-06-24 03:02:03 +02:00
flobernd 83ea3bc2c8 Minor bugfixes 2017-06-24 02:48:14 +02:00
flobernd 39bdaeeeb9 Some changes to the instruction-formatter 2017-06-24 02:16:16 +02:00
flobernd 0957a57ab4 Fixed vector-length for EVEX instructions with fixed vector-length 2017-06-24 00:01:21 +02:00
flobernd b3d508850f Added information for VEX/EVEX/MVEX instructions with static broadcast-factor 2017-06-23 20:47:34 +02:00
flobernd cd3bf5586b Changed default element-count from 0 to 1 2017-06-23 04:26:21 +02:00
flobernd c8c3d29ba4 Added support for MVEX instructions with static broadcast factor 2017-06-23 03:35:12 +02:00
flobernd 2297c763cf Added compressed disp8 calculation for MVEX instructions with element-granularity 2017-06-23 01:40:19 +02:00
flobernd d8f3843f57 Added compressed disp8 calculation for MVEX instructions without swizzle/broadcast/convert functionality 2017-06-23 01:15:42 +02:00
flobernd 6c370d29c9 Added support for some MVEX special-cases 2017-06-22 22:10:18 +02:00
flobernd 4d3a71369b Removed EVEX tuple-type and element-size from the public info-struct 2017-06-22 19:54:35 +02:00
flobernd b9c43d83a7 Added compressed disp8 calculation for MVEX instructions 2017-06-22 19:39:43 +02:00
flobernd 76f0bcf00d Improved semantic decoding of MVEX instructions 2017-06-22 19:14:27 +02:00
flobernd 2a0525925f Added decoding of MVEX swizzle/conversion and rounding-control values 2017-06-22 02:42:16 +02:00
flobernd 5bd81b7f1c Fixed sign-extension of displacement values 2017-06-22 01:38:41 +02:00
flobernd 433ca68926 Fixed formatting of sign-extended immediate operands 2017-06-21 18:30:11 +02:00
flobernd bd38d86986 Updated CMake file and Zydis features 2017-06-21 18:25:53 +02:00
flobernd dc62509b9b Ignore REX-prefix, if it is not the last prefix before the opcode 2017-06-21 04:04:58 +02:00
flobernd 9628fb8367 Fixed order of segment-registers 2017-06-21 03:03:13 +02:00
flobernd 6ff954f585 Fixed MVEX.SSS error-condition 2017-06-20 22:56:25 +02:00
flobernd d475231a63 Fixed decoding of implicit "1" immediate (ROL, ROR, RCL, ...) 2017-06-20 22:44:37 +02:00
flobernd 5112e61fd8 Fixed element-type for AGEN operands 2017-06-20 22:02:40 +02:00
flobernd 52e1b59702 Improved EVEX and MVEX encoding 
- Added some MASK related error-conditions
- Added functionality and mask-policy attributes to the MVEX instruction-definition struct
- Added MVEX specific error-condition
 2017-06-20 21:23:06 +02:00
flobernd 95b685a29d Minor bugfixes 
- Fixed some VEX/EVEX/MVEX-prefix error conditions
- MASK register size is now 64-bit for EVEX- and 16-bit for MVEX-instructions
 2017-06-20 17:48:55 +02:00
flobernd 17358016d9 Allowed custom operand-sizes for register operands 2017-06-20 03:16:17 +02:00
flobernd ee97ae753c Fixed some EVEX tuple-types 2017-06-19 20:46:42 +02:00
flobernd 4bceac86c9 Various bugfixes 
- Fixed operand-size and element-count of AGEN operands
- Fixed decoding of 8-bit modrm.rm register-operands
- Fixed vector-length for EVEX instructions with rounding-semantics
 2017-06-19 20:19:21 +02:00
flobernd 2d2e1acf27 Added T1_4X tuple-type 2017-06-18 22:02:59 +02:00
flobernd f20dc484cd Fixed priority of mandatory-prefixes 2017-06-17 21:01:57 +02:00
flobernd 58b15163f2 Improved decoding of PTR and AGEN operands 2017-06-17 02:50:08 +02:00
flobernd 6794495f63 Various bugfixes 
- Fixed decoding of XOP/VEX instructions with 256-bit vector length
- Fixed decoding of instructions with hardcoded displacement values (e.g. MOFFS)
- Fixed decoding of instructions that make use of the "ANY" mandatory-prefix filter
 2017-06-17 00:59:42 +02:00
flobernd 1d023c2997 Implemented decoding of PTR and AGEN operands 2017-06-17 00:20:44 +02:00
flobernd ad35e81eee Added semantic element-information for operands 2017-06-16 23:19:57 +02:00
flobernd 44792f2338 Added semantic decoding of implicit memory operands 2017-06-16 16:27:37 +02:00
flobernd 1db4db9ec2 Added semantic decoding of implicit register operands 2017-06-16 03:25:39 +02:00
flobernd 6caa68b674 Reimplemented decoding of 3DNOW instructions and improved EVEX decoding 2017-06-13 22:04:29 +02:00
flobernd 702f6b8d53 Reimplemented a basic version of semantic operand-decoding 2017-06-13 20:17:20 +02:00
flobernd 26d39cc7f0 Fixed XOP decoding 2017-06-12 21:07:43 +02:00
flobernd 8740b1e50f Major changes to the instruction decoder 
- Decoupled semantic operand decoding (optional) from physical instruction decoding
- Several optimizations of the internal structures
- Further preparations for MVEX-support
 2017-06-12 19:16:01 +02:00
Joel Höner d3192a8be7 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-05-05 19:26:13 +02:00
Joel Höner de666d7a4a Improved handling of unreachable code 2017-05-05 19:26:03 +02:00
flobernd baa1bc243a Fixed decoding of VEX/EVEX instructions with high-register-specifiers 2017-04-25 17:46:02 +02:00
Joel Höner 40d6c39dbe Renamed disassembler mode constants 
ZYDIS_DISASSEMBLER_MODE_* -> ZYDIS_OPERATING_MODE_*
 2017-04-12 21:12:18 +02:00
flobernd 71a6d786d7 Minor bugfixes and cosmetical changes 2017-04-12 21:00:46 +02:00
Joel Höner ebf71d632f Moved `internal` sub-struct from info to context 
Also, fixed examples and tools.
 2017-04-11 03:18:08 +02:00
Joel Höner 71a551ef1a Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-04-11 02:20:02 +02:00
Joel Höner c9606c389d Removed obsolete public decoder struct 2017-04-11 02:19:53 +02:00
flobernd 8dd599555f Further improvements on #13 2017-04-09 23:11:16 +02:00
Joel Höner 3b47ed4a9a Fixed inaccurate relative operands on decoding 
Resolves #13
 2017-04-09 20:55:49 +02:00
Joel Höner fda4f15c6d Many encoder bug-fixes, movabs support 2017-01-23 21:52:26 +01:00
Joel Höner 616cd00ec8 Encoder support for rIP relative addressing 2017-01-23 19:21:15 +01:00
Joel Höner 0862398940 Various encoder bug-fixes 2017-01-23 18:31:50 +01:00
Joel Höner 781b9641c4 Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-01-23 01:37:45 +01:00
flobernd 8157b9fa42 Temporary change to expose the semantic operand-type 2017-01-23 01:17:15 +01:00
Joel Höner 4fe029a34e Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-01-22 22:12:24 +01:00
Joel Höner eb64a23231 Added encoding of opcode bits into ModRM 2017-01-22 22:12:06 +01:00
flobernd deff3b8e55 Fixed register encoding 2017-01-22 21:44:42 +01:00
Joel Höner 1faec66a66 Fixed mandatory prefixes, added prefix compatibility checks 2017-01-22 19:02:07 +01:00
Joel Höner cb98db80ea Minor encoder cleanup 2017-01-22 17:38:14 +01:00
Joel Höner 587187af89 Implemented address size prefix encoding, bugfixes 2017-01-22 15:46:20 +01:00
Joel Höner b3c8d44bda Implemented segment prefix encoding, refactoring 
- Moved memory operand encoding into dedicated function
 2017-01-21 23:53:50 +01:00
Joel Höner 87e80346f4 Fixed tools 2017-01-21 18:15:37 +01:00
Joel Höner 03e26408fe Merge branch 'develop' of https://github.com/zyantific/zyan-disassembler-engine into develop 2017-01-21 01:48:35 +01:00
Joel Höner 0a50bb9daa Implemented encoding for XOP, VEX and EVEX 2017-01-20 21:18:13 +01:00
Joel Höner 46077709f8 Completed SIB encoding 2017-01-20 00:54:48 +01:00
flobernd 98d34d0c62 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-01-20 00:03:28 +01:00
flobernd dc70ee7eb2 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-01-20 00:02:21 +01:00
flobernd 4b54158aa2 Minor bugfixes 2017-01-20 00:01:56 +01:00
Joel Höner c0f53a3a69 More encoder progress, minor refactoring 
- Added encoding support for more X86 features (IMMs, SIB, ..)
- Added ZYDIS_ARRAY_SIZE macro
- Moved ZYDIS_MAX_INSTRUCTION_LENGTH (Decoder.h -> InstructionInfo.h)
- Renamed ZydisInstructionEncoder -> ZydisEncoderContext
- Various bug-fixes
 2017-01-19 17:37:05 +01:00
Joel Höner 14848083ae More encoder progress 2017-01-17 20:53:34 +01:00
flobernd 5ead1d9345 Minor refactorings 
- The instruction pointer is now directly passed to the ZydisDecoderDecodeInstruction function
- Removed the user-data pointer in the ZydisOperandInfo struct
 2017-01-12 20:14:12 +01:00
Joel Höner 689708fbd3 Refactored docstrings to use uppercase abbreviations 2017-01-12 19:37:57 +01:00
Joel Höner a9514fbfea Minor documentation and style fixes 2017-01-12 18:54:16 +01:00
Joel Höner 0793090388 Implemented basic prefix encoding 2017-01-12 18:53:28 +01:00
Joel Höner 3d2365b6ed Added encoder stub, made decoder input const 2017-01-12 15:12:09 +01:00
flobernd 5af25eee4b Fixed a bug in ZYDIS_CHECK that caused functions to run more than once on certain conditions 2017-01-11 17:29:26 +01:00
flobernd c0528d5cb0 Exposed ZYDIS_MAX_INSTRUCTION_LENGTH constant 2017-01-11 11:24:10 +01:00
flobernd 4165c3b9b2 Removed Input-struct. The input buffer is now directly passed to the ZydisDecodeInstruction function. 2017-01-11 11:20:24 +01:00
Joel Höner b291c8a760 Use size_t instead of uint64_t for memory input 2017-01-07 00:29:16 +01:00
flobernd 5b63557f3c Fixed decoding of instructions with EVEX high-16 register specifiers (R', X, V') 2016-12-05 21:06:29 +01:00
flobernd d4dd176438 Refactorings and bugfixes 
- Added support for the BOUND prefix
- Added support for more detailed operand-actions (read, write, readwrite, cond. read, cond. write, read + cond. write, write + cond. read)
- Added operand-visibility info (explicit, implicit, hidden)
- Fixed some bugs in the prefix-decoding routines
- Removed stdbool.h dependency and introduced custom boolean-type for better portability
 2016-12-05 02:24:01 +01:00
flobernd fbbbcbadb8 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2016-11-28 19:58:01 +01:00
Joel Höner f4959072dc Renamed ZydisFormatFlags -> ZydisFormatterFlags 2016-11-28 19:13:01 +01:00
Joel Höner 4e78d04788 Fixed lib build with clang, fixed tools 2016-11-28 18:56:39 +01:00
flobernd bfcbe3e8c1 Minor bugfixes and refactorings 2016-11-28 15:03:39 +01:00
flobernd 477a908bb0 Added more formatter-hooks 
- ZYDIS_FORMATTER_HOOK_PRINT_DISPLACEMENT
- ZYDIS_FORMATTER_HOOK_PRINT_IMMEDIATE
 2016-11-28 11:14:47 +01:00
flobernd 9a0b1da975 Added missing registers and CPUID feature-flags 2016-11-27 23:24:43 +01:00
flobernd e481c3e401 Minor refactorings and changes to the instruction-formatter 
- The formatter now makes use of the format-macros in inttypes.h for better portability
- Added formatter-hook ZYDIS_FORMATTER_HOOK_PRINT_SEGMENT
 2016-11-26 18:41:58 +01:00
flobernd 816bb570c7 Complete rewrite of the instruction-formatter 
- Added hooking functionality to support custom instruction-formatting
- Added FormatterHooks demo that demonstrates the hooking functionality

InstructionEditor:
- Fixed issues with still non-deterministic output on code-generation
 2016-11-26 13:08:37 +01:00
flobernd 7f1c0bd8f1 Minor refactorings and bugfixes 2016-11-24 10:57:23 +01:00
flobernd 7f7cbd8dcd Internal changes and optimizations of the generated tables and the InstructionEditor 2016-11-22 18:12:05 +01:00
flobernd be56ef937d Minor bugfixes and refactorings 2016-11-21 14:55:17 +01:00
flobernd c4dce1adb9 Added support for test-register operands (TR0..TR7) 
- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
 2016-11-14 03:39:17 +01:00
flobernd 58c73b2885 Bugfixes and Support for some more registers 
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
 2016-11-14 02:10:59 +01:00
flobernd 3f09ffca69 Minor refactorings and further preparation for advanced features 2016-11-11 22:03:26 +01:00