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Fixed register decoding for XOP and VEX instructions (again)

This commit is contained in:
flobernd 2017-06-28 20:50:32 +02:00
parent 808ccac372
commit 05817fa8e7
1 changed files with 13 additions and 7 deletions
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20
src/Decoder.c
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@ -980,14 +980,20 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REG_ENCODING_IS4: case ZYDIS_REG_ENCODING_IS4:
{ {
uint8_t value = (info->details.imm[0].value.ubyte >> 4) & 0x0F; uint8_t value = (info->details.imm[0].value.ubyte >> 4) & 0x0F;
switch (registerClass) // We have to check the instruction-encoding, because the extension by bit [3] is only
// valid for EVEX and MVEX instructions
if ((info->encoding == ZYDIS_INSTRUCTION_ENCODING_EVEX) ||
(info->encoding == ZYDIS_INSTRUCTION_ENCODING_MVEX))
{ {
case ZYDIS_REGCLASS_XMM: switch (registerClass)
case ZYDIS_REGCLASS_YMM: {
case ZYDIS_REGCLASS_ZMM: case ZYDIS_REGCLASS_XMM:
value |= (((info->details.imm[0].value.ubyte >> 3) & 0x01) << 4); case ZYDIS_REGCLASS_YMM:
default: case ZYDIS_REGCLASS_ZMM:
break; value |= (((info->details.imm[0].value.ubyte >> 3) & 0x01) << 4);
default:
break;
}
} }
return value; return value;
} }