From 05817fa8e718d5c66bc87a9fcb77a0e8c87c7d24 Mon Sep 17 00:00:00 2001 From: flobernd Date: Wed, 28 Jun 2017 20:50:32 +0200 Subject: [PATCH] Fixed register decoding for XOP and VEX instructions (again) --- src/Decoder.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/Decoder.c b/src/Decoder.c index 4cfcfc5..bb9c563 100644 --- a/src/Decoder.c +++ b/src/Decoder.c @@ -980,14 +980,20 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio case ZYDIS_REG_ENCODING_IS4: { uint8_t value = (info->details.imm[0].value.ubyte >> 4) & 0x0F; - switch (registerClass) + // We have to check the instruction-encoding, because the extension by bit [3] is only + // valid for EVEX and MVEX instructions + if ((info->encoding == ZYDIS_INSTRUCTION_ENCODING_EVEX) || + (info->encoding == ZYDIS_INSTRUCTION_ENCODING_MVEX)) { - case ZYDIS_REGCLASS_XMM: - case ZYDIS_REGCLASS_YMM: - case ZYDIS_REGCLASS_ZMM: - value |= (((info->details.imm[0].value.ubyte >> 3) & 0x01) << 4); - default: - break; + switch (registerClass) + { + case ZYDIS_REGCLASS_XMM: + case ZYDIS_REGCLASS_YMM: + case ZYDIS_REGCLASS_ZMM: + value |= (((info->details.imm[0].value.ubyte >> 3) & 0x01) << 4); + default: + break; + } } return value; }