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zydis
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Fixed register decoding for XOP and VEX instructions (again)

This commit is contained in:
flobernd 2017-06-28 20:50:32 +02:00
parent 808ccac372
commit 05817fa8e7
1 changed files with 13 additions and 7 deletions
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6
src/Decoder.c
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@ -980,6 +980,11 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REG_ENCODING_IS4: case ZYDIS_REG_ENCODING_IS4:
{ {
uint8_t value = (info->details.imm[0].value.ubyte >> 4) & 0x0F; uint8_t value = (info->details.imm[0].value.ubyte >> 4) & 0x0F;
// We have to check the instruction-encoding, because the extension by bit [3] is only
// valid for EVEX and MVEX instructions
if ((info->encoding == ZYDIS_INSTRUCTION_ENCODING_EVEX) ||
(info->encoding == ZYDIS_INSTRUCTION_ENCODING_MVEX))
{
switch (registerClass) switch (registerClass)
{ {
case ZYDIS_REGCLASS_XMM: case ZYDIS_REGCLASS_XMM:
@ -989,6 +994,7 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
default: default:
break; break;
} }
}
return value; return value;
} }
case ZYDIS_REG_ENCODING_MASK: case ZYDIS_REG_ENCODING_MASK: