zydis/assets
flobernd 58c73b2885 Bugfixes and Support for some more registers
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
2016-11-14 02:10:59 +01:00
..
InstructionEditor Bugfixes and Support for some more registers 2016-11-14 02:10:59 +01:00
instructions.json Bugfixes and Support for some more registers 2016-11-14 02:10:59 +01:00