mirror of https://github.com/x64dbg/zydis
1756 lines
42 KiB
C++
1756 lines
42 KiB
C++
/***************************************************************************************************
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Zyan Disassembler Engine
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Version 1.0
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Remarks : Freeware, Copyright must be included
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Original Author : Florian Bernd
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Modifications : Joel Höner
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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***************************************************************************************************/
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#ifndef _ZYDIS_OPCODETABLE_HPP_
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#define _ZYDIS_OPCODETABLE_HPP_
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#include <stdint.h>
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#include <cassert>
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namespace Zydis
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{
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/**
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* @brief Values that represent an instruction mnemonic.
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*/
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enum class InstructionMnemonic : uint16_t
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{
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/* 000 */ INVALID,
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/* 001 */ AAA,
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/* 002 */ AAD,
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/* 003 */ AAM,
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/* 004 */ AAS,
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/* 005 */ ADC,
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/* 006 */ ADD,
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/* 007 */ ADDPD,
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/* 008 */ ADDPS,
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/* 009 */ ADDSD,
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/* 00A */ ADDSS,
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/* 00B */ ADDSUBPD,
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/* 00C */ ADDSUBPS,
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/* 00D */ AESDEC,
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/* 00E */ AESDECLAST,
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/* 00F */ AESENC,
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/* 010 */ AESENCLAST,
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/* 011 */ AESIMC,
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/* 012 */ AESKEYGENASSIST,
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/* 013 */ AND,
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/* 014 */ ANDNPD,
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/* 015 */ ANDNPS,
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/* 016 */ ANDPD,
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/* 017 */ ANDPS,
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/* 018 */ ARPL,
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/* 019 */ BLENDPD,
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/* 01A */ BLENDPS,
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/* 01B */ BLENDVPD,
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/* 01C */ BLENDVPS,
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/* 01D */ BOUND,
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/* 01E */ BSF,
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/* 01F */ BSR,
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/* 020 */ BSWAP,
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/* 021 */ BT,
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/* 022 */ BTC,
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/* 023 */ BTR,
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/* 024 */ BTS,
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/* 025 */ CALL,
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/* 026 */ CBW,
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/* 027 */ CDQ,
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/* 028 */ CDQE,
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/* 029 */ CLC,
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/* 02A */ CLD,
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/* 02B */ CLFLUSH,
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/* 02C */ CLGI,
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/* 02D */ CLI,
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/* 02E */ CLTS,
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/* 02F */ CMC,
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/* 030 */ CMOVA,
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/* 031 */ CMOVAE,
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/* 032 */ CMOVB,
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/* 033 */ CMOVBE,
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/* 034 */ CMOVE,
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/* 035 */ CMOVG,
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/* 036 */ CMOVGE,
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/* 037 */ CMOVL,
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/* 038 */ CMOVLE,
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/* 039 */ CMOVNE,
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/* 03A */ CMOVNO,
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/* 03B */ CMOVNP,
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/* 03C */ CMOVNS,
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/* 03D */ CMOVO,
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/* 03E */ CMOVP,
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/* 03F */ CMOVS,
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/* 040 */ CMP,
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/* 041 */ CMPPD,
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/* 042 */ CMPPS,
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/* 043 */ CMPSB,
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/* 044 */ CMPSD,
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/* 045 */ CMPSQ,
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/* 046 */ CMPSS,
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/* 047 */ CMPSW,
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/* 048 */ CMPXCHG,
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/* 049 */ CMPXCHG16B,
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/* 04A */ CMPXCHG8B,
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/* 04B */ COMISD,
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/* 04C */ COMISS,
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/* 04D */ CPUID,
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/* 04E */ CQO,
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/* 04F */ CRC32,
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/* 050 */ CVTDQ2PD,
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/* 051 */ CVTDQ2PS,
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/* 052 */ CVTPD2DQ,
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/* 053 */ CVTPD2PI,
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/* 054 */ CVTPD2PS,
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/* 055 */ CVTPI2PD,
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/* 056 */ CVTPI2PS,
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/* 057 */ CVTPS2DQ,
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/* 058 */ CVTPS2PD,
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/* 059 */ CVTPS2PI,
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/* 05A */ CVTSD2SI,
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/* 05B */ CVTSD2SS,
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/* 05C */ CVTSI2SD,
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/* 05D */ CVTSI2SS,
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/* 05E */ CVTSS2SD,
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/* 05F */ CVTSS2SI,
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/* 060 */ CVTTPD2DQ,
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/* 061 */ CVTTPD2PI,
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/* 062 */ CVTTPS2DQ,
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/* 063 */ CVTTPS2PI,
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/* 064 */ CVTTSD2SI,
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/* 065 */ CVTTSS2SI,
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/* 066 */ CWD,
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/* 067 */ CWDE,
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/* 068 */ DAA,
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/* 069 */ DAS,
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/* 06A */ DEC,
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/* 06B */ DIV,
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/* 06C */ DIVPD,
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/* 06D */ DIVPS,
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/* 06E */ DIVSD,
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/* 06F */ DIVSS,
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/* 070 */ DPPD,
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/* 071 */ DPPS,
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/* 072 */ EMMS,
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/* 073 */ ENTER,
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/* 074 */ EXTRACTPS,
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/* 075 */ F2XM1,
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/* 076 */ FABS,
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/* 077 */ FADD,
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/* 078 */ FADDP,
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/* 079 */ FBLD,
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/* 07A */ FBSTP,
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/* 07B */ FCHS,
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/* 07C */ FCLEX,
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/* 07D */ FCMOVB,
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/* 07E */ FCMOVBE,
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/* 07F */ FCMOVE,
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/* 080 */ FCMOVNB,
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/* 081 */ FCMOVNBE,
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/* 082 */ FCMOVNE,
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/* 083 */ FCMOVNU,
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/* 084 */ FCMOVU,
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/* 085 */ FCOM,
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/* 086 */ FCOM2,
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/* 087 */ FCOMI,
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/* 088 */ FCOMIP,
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/* 089 */ FCOMP,
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/* 08A */ FCOMP3,
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/* 08B */ FCOMP5,
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/* 08C */ FCOMPP,
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/* 08D */ FCOS,
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/* 08E */ FDECSTP,
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/* 08F */ FDIV,
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/* 090 */ FDIVP,
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/* 091 */ FDIVR,
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/* 092 */ FDIVRP,
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/* 093 */ FEMMS,
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/* 094 */ FFREE,
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/* 095 */ FFREEP,
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/* 096 */ FIADD,
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/* 097 */ FICOM,
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/* 098 */ FICOMP,
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/* 099 */ FIDIV,
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/* 09A */ FIDIVR,
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/* 09B */ FILD,
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/* 09C */ FIMUL,
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/* 09D */ FINCSTP,
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/* 09E */ FIST,
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/* 09F */ FISTP,
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/* 0A0 */ FISTTP,
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/* 0A1 */ FISUB,
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/* 0A2 */ FISUBR,
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/* 0A3 */ FLD,
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/* 0A4 */ FLD1,
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/* 0A5 */ FLDCW,
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/* 0A6 */ FLDENV,
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/* 0A7 */ FLDL2E,
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/* 0A8 */ FLDL2T,
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/* 0A9 */ FLDLG2,
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/* 0AA */ FLDLN2,
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/* 0AB */ FLDPI,
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/* 0AC */ FLDZ,
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/* 0AD */ FMUL,
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/* 0AE */ FMULP,
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/* 0AF */ FNDISI,
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/* 0B0 */ FNENI,
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/* 0B1 */ FNINIT,
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/* 0B2 */ FNOP,
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/* 0B3 */ FNSAVE,
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/* 0B4 */ FNSETPM,
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/* 0B5 */ FNSTCW,
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/* 0B6 */ FNSTENV,
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/* 0B7 */ FNSTSW,
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/* 0B8 */ FPATAN,
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/* 0B9 */ FPREM,
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/* 0BA */ FPREM1,
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/* 0BB */ FPTAN,
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/* 0BC */ FRNDINT,
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/* 0BD */ FRSTOR,
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/* 0BE */ FRSTPM,
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/* 0BF */ FSCALE,
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/* 0C0 */ FSIN,
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/* 0C1 */ FSINCOS,
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/* 0C2 */ FSQRT,
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/* 0C3 */ FST,
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/* 0C4 */ FSTP,
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/* 0C5 */ FSTP1,
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/* 0C6 */ FSTP8,
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/* 0C7 */ FSTP9,
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/* 0C8 */ FSUB,
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/* 0C9 */ FSUBP,
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/* 0CA */ FSUBR,
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/* 0CB */ FSUBRP,
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/* 0CC */ FTST,
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/* 0CD */ FUCOM,
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/* 0CE */ FUCOMI,
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/* 0CF */ FUCOMIP,
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/* 0D0 */ FUCOMP,
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/* 0D1 */ FUCOMPP,
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/* 0D2 */ FXAM,
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/* 0D3 */ FXCH,
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/* 0D4 */ FXCH4,
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/* 0D5 */ FXCH7,
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/* 0D6 */ FXRSTOR,
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/* 0D7 */ FXSAVE,
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/* 0D8 */ FXTRACT,
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/* 0D9 */ FYL2X,
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/* 0DA */ FYL2XP1,
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/* 0DB */ GETSEC,
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/* 0DC */ HADDPD,
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/* 0DD */ HADDPS,
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/* 0DE */ HLT,
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/* 0DF */ HSUBPD,
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/* 0E0 */ HSUBPS,
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/* 0E1 */ IDIV,
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/* 0E2 */ IMUL,
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/* 0E3 */ IN,
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/* 0E4 */ INC,
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/* 0E5 */ INSB,
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/* 0E6 */ INSD,
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/* 0E7 */ INSERTPS,
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/* 0E8 */ INSW,
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/* 0E9 */ INT,
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/* 0EA */ INT1,
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/* 0EB */ INT3,
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/* 0EC */ INTO,
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/* 0ED */ INVD,
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/* 0EE */ INVEPT,
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/* 0EF */ INVLPG,
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/* 0F0 */ INVLPGA,
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/* 0F1 */ INVVPID,
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/* 0F2 */ IRETD,
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/* 0F3 */ IRETQ,
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/* 0F4 */ IRETW,
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/* 0F5 */ JA,
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/* 0F6 */ JB,
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/* 0F7 */ JBE,
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/* 0F8 */ JCXZ,
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/* 0F9 */ JE,
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/* 0FA */ JECXZ,
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/* 0FB */ JG,
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/* 0FC */ JGE,
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/* 0FD */ JL,
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/* 0FE */ JLE,
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/* 0FF */ JMP,
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/* 100 */ JNB,
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/* 101 */ JNE,
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/* 102 */ JNO,
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/* 103 */ JNP,
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/* 104 */ JNS,
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/* 105 */ JO,
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/* 106 */ JP,
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/* 107 */ JRCXZ,
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/* 108 */ JS,
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/* 109 */ LAHF,
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/* 10A */ LAR,
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/* 10B */ LDDQU,
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/* 10C */ LDMXCSR,
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/* 10D */ LDS,
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/* 10E */ LEA,
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/* 10F */ LEAVE,
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/* 110 */ LES,
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/* 111 */ LFENCE,
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/* 112 */ LFS,
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/* 113 */ LGDT,
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/* 114 */ LGS,
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/* 115 */ LIDT,
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/* 116 */ LLDT,
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/* 117 */ LMSW,
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/* 118 */ LOCK,
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/* 119 */ LODSB,
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/* 11A */ LODSD,
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/* 11B */ LODSQ,
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/* 11C */ LODSW,
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/* 11D */ LOOP,
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/* 11E */ LOOPE,
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/* 11F */ LOOPNE,
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/* 120 */ LSL,
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/* 121 */ LSS,
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/* 122 */ LTR,
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/* 123 */ MASKMOVDQU,
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/* 124 */ MASKMOVQ,
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/* 125 */ MAXPD,
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/* 126 */ MAXPS,
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/* 127 */ MAXSD,
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/* 128 */ MAXSS,
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/* 129 */ MFENCE,
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/* 12A */ MINPD,
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/* 12B */ MINPS,
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/* 12C */ MINSD,
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/* 12D */ MINSS,
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/* 12E */ MONITOR,
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/* 12F */ MONTMUL,
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/* 130 */ MOV,
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/* 131 */ MOVAPD,
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/* 132 */ MOVAPS,
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/* 133 */ MOVBE,
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/* 134 */ MOVD,
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/* 135 */ MOVDDUP,
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/* 136 */ MOVDQ2Q,
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/* 137 */ MOVDQA,
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/* 138 */ MOVDQU,
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/* 139 */ MOVHLPS,
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/* 13A */ MOVHPD,
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/* 13B */ MOVHPS,
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/* 13C */ MOVLHPS,
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/* 13D */ MOVLPD,
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/* 13E */ MOVLPS,
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/* 13F */ MOVMSKPD,
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/* 140 */ MOVMSKPS,
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/* 141 */ MOVNTDQ,
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/* 142 */ MOVNTDQA,
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/* 143 */ MOVNTI,
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/* 144 */ MOVNTPD,
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/* 145 */ MOVNTPS,
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/* 146 */ MOVNTQ,
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/* 147 */ MOVQ,
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/* 148 */ MOVQ2DQ,
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/* 149 */ MOVSB,
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/* 14A */ MOVSD,
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/* 14B */ MOVSHDUP,
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/* 14C */ MOVSLDUP,
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/* 14D */ MOVSQ,
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/* 14E */ MOVSS,
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/* 14F */ MOVSW,
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/* 150 */ MOVSX,
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/* 151 */ MOVSXD,
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/* 152 */ MOVUPD,
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/* 153 */ MOVUPS,
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/* 154 */ MOVZX,
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/* 155 */ MPSADBW,
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/* 156 */ MUL,
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/* 157 */ MULPD,
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/* 158 */ MULPS,
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/* 159 */ MULSD,
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/* 15A */ MULSS,
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/* 15B */ MWAIT,
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/* 15C */ NEG,
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/* 15D */ NOP,
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/* 15E */ NOT,
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/* 15F */ OR,
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/* 160 */ ORPD,
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/* 161 */ ORPS,
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/* 162 */ OUT,
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/* 163 */ OUTSB,
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/* 164 */ OUTSD,
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/* 165 */ OUTSW,
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/* 166 */ PABSB,
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/* 167 */ PABSD,
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/* 168 */ PABSW,
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/* 169 */ PACKSSDW,
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/* 16A */ PACKSSWB,
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/* 16B */ PACKUSDW,
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/* 16C */ PACKUSWB,
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/* 16D */ PADDB,
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/* 16E */ PADDD,
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/* 16F */ PADDQ,
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/* 170 */ PADDSB,
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/* 171 */ PADDSW,
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/* 172 */ PADDUSB,
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/* 173 */ PADDUSW,
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/* 174 */ PADDW,
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/* 175 */ PALIGNR,
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/* 176 */ PAND,
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/* 177 */ PANDN,
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/* 178 */ PAUSE,
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/* 179 */ PAVGB,
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/* 17A */ PAVGUSB,
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/* 17B */ PAVGW,
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/* 17C */ PBLENDVB,
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/* 17D */ PBLENDW,
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/* 17E */ PCLMULQDQ,
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/* 17F */ PCMPEQB,
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/* 180 */ PCMPEQD,
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/* 181 */ PCMPEQQ,
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/* 182 */ PCMPEQW,
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/* 183 */ PCMPESTRI,
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/* 184 */ PCMPESTRM,
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/* 185 */ PCMPGTB,
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/* 186 */ PCMPGTD,
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/* 187 */ PCMPGTQ,
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/* 188 */ PCMPGTW,
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/* 189 */ PCMPISTRI,
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/* 18A */ PCMPISTRM,
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/* 18B */ PEXTRB,
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/* 18C */ PEXTRD,
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/* 18D */ PEXTRQ,
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/* 18E */ PEXTRW,
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/* 18F */ PF2ID,
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/* 190 */ PF2IW,
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/* 191 */ PFACC,
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/* 192 */ PFADD,
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/* 193 */ PFCMPEQ,
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/* 194 */ PFCMPGE,
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/* 195 */ PFCMPGT,
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/* 196 */ PFMAX,
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/* 197 */ PFMIN,
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/* 198 */ PFMUL,
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/* 199 */ PFNACC,
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/* 19A */ PFPNACC,
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/* 19B */ PFRCP,
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/* 19C */ PFRCPIT1,
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/* 19D */ PFRCPIT2,
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/* 19E */ PFRSQIT1,
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/* 19F */ PFRSQRT,
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/* 1A0 */ PFSUB,
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/* 1A1 */ PFSUBR,
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/* 1A2 */ PHADDD,
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/* 1A3 */ PHADDSW,
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/* 1A4 */ PHADDW,
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/* 1A5 */ PHMINPOSUW,
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/* 1A6 */ PHSUBD,
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/* 1A7 */ PHSUBSW,
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/* 1A8 */ PHSUBW,
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/* 1A9 */ PI2FD,
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/* 1AA */ PI2FW,
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/* 1AB */ PINSRB,
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/* 1AC */ PINSRD,
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/* 1AD */ PINSRQ,
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/* 1AE */ PINSRW,
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/* 1AF */ PMADDUBSW,
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/* 1B0 */ PMADDWD,
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/* 1B1 */ PMAXSB,
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/* 1B2 */ PMAXSD,
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/* 1B3 */ PMAXSW,
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/* 1B4 */ PMAXUB,
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/* 1B5 */ PMAXUD,
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/* 1B6 */ PMAXUW,
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/* 1B7 */ PMINSB,
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/* 1B8 */ PMINSD,
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/* 1B9 */ PMINSW,
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/* 1BA */ PMINUB,
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/* 1BB */ PMINUD,
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/* 1BC */ PMINUW,
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/* 1BD */ PMOVMSKB,
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/* 1BE */ PMOVSXBD,
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/* 1BF */ PMOVSXBQ,
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/* 1C0 */ PMOVSXBW,
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/* 1C1 */ PMOVSXDQ,
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/* 1C2 */ PMOVSXWD,
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/* 1C3 */ PMOVSXWQ,
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/* 1C4 */ PMOVZXBD,
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/* 1C5 */ PMOVZXBQ,
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/* 1C6 */ PMOVZXBW,
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/* 1C7 */ PMOVZXDQ,
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/* 1C8 */ PMOVZXWD,
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/* 1C9 */ PMOVZXWQ,
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/* 1CA */ PMULDQ,
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/* 1CB */ PMULHRSW,
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/* 1CC */ PMULHRW,
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/* 1CD */ PMULHUW,
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/* 1CE */ PMULHW,
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/* 1CF */ PMULLD,
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/* 1D0 */ PMULLW,
|
|
/* 1D1 */ PMULUDQ,
|
|
/* 1D2 */ POP,
|
|
/* 1D3 */ POPA,
|
|
/* 1D4 */ POPAD,
|
|
/* 1D5 */ POPCNT,
|
|
/* 1D6 */ POPFD,
|
|
/* 1D7 */ POPFQ,
|
|
/* 1D8 */ POPFW,
|
|
/* 1D9 */ POR,
|
|
/* 1DA */ PREFETCH,
|
|
/* 1DB */ PREFETCHNTA,
|
|
/* 1DC */ PREFETCHT0,
|
|
/* 1DD */ PREFETCHT1,
|
|
/* 1DE */ PREFETCHT2,
|
|
/* 1DF */ PSADBW,
|
|
/* 1E0 */ PSHUFB,
|
|
/* 1E1 */ PSHUFD,
|
|
/* 1E2 */ PSHUFHW,
|
|
/* 1E3 */ PSHUFLW,
|
|
/* 1E4 */ PSHUFW,
|
|
/* 1E5 */ PSIGNB,
|
|
/* 1E6 */ PSIGND,
|
|
/* 1E7 */ PSIGNW,
|
|
/* 1E8 */ PSLLD,
|
|
/* 1E9 */ PSLLDQ,
|
|
/* 1EA */ PSLLQ,
|
|
/* 1EB */ PSLLW,
|
|
/* 1EC */ PSRAD,
|
|
/* 1ED */ PSRAW,
|
|
/* 1EE */ PSRLD,
|
|
/* 1EF */ PSRLDQ,
|
|
/* 1F0 */ PSRLQ,
|
|
/* 1F1 */ PSRLW,
|
|
/* 1F2 */ PSUBB,
|
|
/* 1F3 */ PSUBD,
|
|
/* 1F4 */ PSUBQ,
|
|
/* 1F5 */ PSUBSB,
|
|
/* 1F6 */ PSUBSW,
|
|
/* 1F7 */ PSUBUSB,
|
|
/* 1F8 */ PSUBUSW,
|
|
/* 1F9 */ PSUBW,
|
|
/* 1FA */ PSWAPD,
|
|
/* 1FB */ PTEST,
|
|
/* 1FC */ PUNPCKHBW,
|
|
/* 1FD */ PUNPCKHDQ,
|
|
/* 1FE */ PUNPCKHQDQ,
|
|
/* 1FF */ PUNPCKHWD,
|
|
/* 200 */ PUNPCKLBW,
|
|
/* 201 */ PUNPCKLDQ,
|
|
/* 202 */ PUNPCKLQDQ,
|
|
/* 203 */ PUNPCKLWD,
|
|
/* 204 */ PUSH,
|
|
/* 205 */ PUSHA,
|
|
/* 206 */ PUSHAD,
|
|
/* 207 */ PUSHFD,
|
|
/* 208 */ PUSHFQ,
|
|
/* 209 */ PUSHFW,
|
|
/* 20A */ PXOR,
|
|
/* 20B */ RCL,
|
|
/* 20C */ RCPPS,
|
|
/* 20D */ RCPSS,
|
|
/* 20E */ RCR,
|
|
/* 20F */ RDMSR,
|
|
/* 210 */ RDPMC,
|
|
/* 211 */ RDRAND,
|
|
/* 212 */ RDTSC,
|
|
/* 213 */ RDTSCP,
|
|
/* 214 */ REP,
|
|
/* 215 */ REPNE,
|
|
/* 216 */ RET,
|
|
/* 217 */ RETF,
|
|
/* 218 */ ROL,
|
|
/* 219 */ ROR,
|
|
/* 21A */ ROUNDPD,
|
|
/* 21B */ ROUNDPS,
|
|
/* 21C */ ROUNDSD,
|
|
/* 21D */ ROUNDSS,
|
|
/* 21E */ RSM,
|
|
/* 21F */ RSQRTPS,
|
|
/* 220 */ RSQRTSS,
|
|
/* 221 */ SAHF,
|
|
/* 222 */ SALC,
|
|
/* 223 */ SAR,
|
|
/* 224 */ SBB,
|
|
/* 225 */ SCASB,
|
|
/* 226 */ SCASD,
|
|
/* 227 */ SCASQ,
|
|
/* 228 */ SCASW,
|
|
/* 229 */ SETA,
|
|
/* 22A */ SETAE,
|
|
/* 22B */ SETB,
|
|
/* 22C */ SETBE,
|
|
/* 22D */ SETE,
|
|
/* 22E */ SETG,
|
|
/* 22F */ SETGE,
|
|
/* 230 */ SETL,
|
|
/* 231 */ SETLE,
|
|
/* 232 */ SETNE,
|
|
/* 233 */ SETNO,
|
|
/* 234 */ SETNP,
|
|
/* 235 */ SETNS,
|
|
/* 236 */ SETO,
|
|
/* 237 */ SETP,
|
|
/* 238 */ SETS,
|
|
/* 239 */ SFENCE,
|
|
/* 23A */ SGDT,
|
|
/* 23B */ SHL,
|
|
/* 23C */ SHLD,
|
|
/* 23D */ SHR,
|
|
/* 23E */ SHRD,
|
|
/* 23F */ SHUFPD,
|
|
/* 240 */ SHUFPS,
|
|
/* 241 */ SIDT,
|
|
/* 242 */ SKINIT,
|
|
/* 243 */ SLDT,
|
|
/* 244 */ SMSW,
|
|
/* 245 */ SQRTPD,
|
|
/* 246 */ SQRTPS,
|
|
/* 247 */ SQRTSD,
|
|
/* 248 */ SQRTSS,
|
|
/* 249 */ STC,
|
|
/* 24A */ STD,
|
|
/* 24B */ STGI,
|
|
/* 24C */ STI,
|
|
/* 24D */ STMXCSR,
|
|
/* 24E */ STOSB,
|
|
/* 24F */ STOSD,
|
|
/* 250 */ STOSQ,
|
|
/* 251 */ STOSW,
|
|
/* 252 */ STR,
|
|
/* 253 */ SUB,
|
|
/* 254 */ SUBPD,
|
|
/* 255 */ SUBPS,
|
|
/* 256 */ SUBSD,
|
|
/* 257 */ SUBSS,
|
|
/* 258 */ SWAPGS,
|
|
/* 259 */ SYSCALL,
|
|
/* 25A */ SYSENTER,
|
|
/* 25B */ SYSEXIT,
|
|
/* 25C */ SYSRET,
|
|
/* 25D */ TEST,
|
|
/* 25E */ UCOMISD,
|
|
/* 25F */ UCOMISS,
|
|
/* 260 */ UD2,
|
|
/* 261 */ UNPCKHPD,
|
|
/* 262 */ UNPCKHPS,
|
|
/* 263 */ UNPCKLPD,
|
|
/* 264 */ UNPCKLPS,
|
|
/* 265 */ VADDPD,
|
|
/* 266 */ VADDPS,
|
|
/* 267 */ VADDSD,
|
|
/* 268 */ VADDSS,
|
|
/* 269 */ VADDSUBPD,
|
|
/* 26A */ VADDSUBPS,
|
|
/* 26B */ VAESDEC,
|
|
/* 26C */ VAESDECLAST,
|
|
/* 26D */ VAESENC,
|
|
/* 26E */ VAESENCLAST,
|
|
/* 26F */ VAESIMC,
|
|
/* 270 */ VAESKEYGENASSIST,
|
|
/* 271 */ VANDNPD,
|
|
/* 272 */ VANDNPS,
|
|
/* 273 */ VANDPD,
|
|
/* 274 */ VANDPS,
|
|
/* 275 */ VBLENDPD,
|
|
/* 276 */ VBLENDPS,
|
|
/* 277 */ VBLENDVPD,
|
|
/* 278 */ VBLENDVPS,
|
|
/* 279 */ VBROADCASTSD,
|
|
/* 27A */ VBROADCASTSS,
|
|
/* 27B */ VCMPPD,
|
|
/* 27C */ VCMPPS,
|
|
/* 27D */ VCMPSD,
|
|
/* 27E */ VCMPSS,
|
|
/* 27F */ VCOMISD,
|
|
/* 280 */ VCOMISS,
|
|
/* 281 */ VCVTDQ2PD,
|
|
/* 282 */ VCVTDQ2PS,
|
|
/* 283 */ VCVTPD2DQ,
|
|
/* 284 */ VCVTPD2PS,
|
|
/* 285 */ VCVTPS2DQ,
|
|
/* 286 */ VCVTPS2PD,
|
|
/* 287 */ VCVTSD2SI,
|
|
/* 288 */ VCVTSD2SS,
|
|
/* 289 */ VCVTSI2SD,
|
|
/* 28A */ VCVTSI2SS,
|
|
/* 28B */ VCVTSS2SD,
|
|
/* 28C */ VCVTSS2SI,
|
|
/* 28D */ VCVTTPD2DQ,
|
|
/* 28E */ VCVTTPS2DQ,
|
|
/* 28F */ VCVTTSD2SI,
|
|
/* 290 */ VCVTTSS2SI,
|
|
/* 291 */ VDIVPD,
|
|
/* 292 */ VDIVPS,
|
|
/* 293 */ VDIVSD,
|
|
/* 294 */ VDIVSS,
|
|
/* 295 */ VDPPD,
|
|
/* 296 */ VDPPS,
|
|
/* 297 */ VERR,
|
|
/* 298 */ VERW,
|
|
/* 299 */ VEXTRACTF128,
|
|
/* 29A */ VEXTRACTPS,
|
|
/* 29B */ VHADDPD,
|
|
/* 29C */ VHADDPS,
|
|
/* 29D */ VHSUBPD,
|
|
/* 29E */ VHSUBPS,
|
|
/* 29F */ VINSERTF128,
|
|
/* 2A0 */ VINSERTPS,
|
|
/* 2A1 */ VLDDQU,
|
|
/* 2A2 */ VMASKMOVDQU,
|
|
/* 2A3 */ VMASKMOVPD,
|
|
/* 2A4 */ VMASKMOVPS,
|
|
/* 2A5 */ VMAXPD,
|
|
/* 2A6 */ VMAXPS,
|
|
/* 2A7 */ VMAXSD,
|
|
/* 2A8 */ VMAXSS,
|
|
/* 2A9 */ VMCALL,
|
|
/* 2AA */ VMCLEAR,
|
|
/* 2AB */ VMINPD,
|
|
/* 2AC */ VMINPS,
|
|
/* 2AD */ VMINSD,
|
|
/* 2AE */ VMINSS,
|
|
/* 2AF */ VMLAUNCH,
|
|
/* 2B0 */ VMLOAD,
|
|
/* 2B1 */ VMMCALL,
|
|
/* 2B2 */ VMOVAPD,
|
|
/* 2B3 */ VMOVAPS,
|
|
/* 2B4 */ VMOVD,
|
|
/* 2B5 */ VMOVDDUP,
|
|
/* 2B6 */ VMOVDQA,
|
|
/* 2B7 */ VMOVDQU,
|
|
/* 2B8 */ VMOVHLPS,
|
|
/* 2B9 */ VMOVHPD,
|
|
/* 2BA */ VMOVHPS,
|
|
/* 2BB */ VMOVLHPS,
|
|
/* 2BC */ VMOVLPD,
|
|
/* 2BD */ VMOVLPS,
|
|
/* 2BE */ VMOVMSKPD,
|
|
/* 2BF */ VMOVMSKPS,
|
|
/* 2C0 */ VMOVNTDQ,
|
|
/* 2C1 */ VMOVNTDQA,
|
|
/* 2C2 */ VMOVNTPD,
|
|
/* 2C3 */ VMOVNTPS,
|
|
/* 2C4 */ VMOVQ,
|
|
/* 2C5 */ VMOVSD,
|
|
/* 2C6 */ VMOVSHDUP,
|
|
/* 2C7 */ VMOVSLDUP,
|
|
/* 2C8 */ VMOVSS,
|
|
/* 2C9 */ VMOVUPD,
|
|
/* 2CA */ VMOVUPS,
|
|
/* 2CB */ VMPSADBW,
|
|
/* 2CC */ VMPTRLD,
|
|
/* 2CD */ VMPTRST,
|
|
/* 2CE */ VMREAD,
|
|
/* 2CF */ VMRESUME,
|
|
/* 2D0 */ VMRUN,
|
|
/* 2D1 */ VMSAVE,
|
|
/* 2D2 */ VMULPD,
|
|
/* 2D3 */ VMULPS,
|
|
/* 2D4 */ VMULSD,
|
|
/* 2D5 */ VMULSS,
|
|
/* 2D6 */ VMWRITE,
|
|
/* 2D7 */ VMXOFF,
|
|
/* 2D8 */ VMXON,
|
|
/* 2D9 */ VORPD,
|
|
/* 2DA */ VORPS,
|
|
/* 2DB */ VPABSB,
|
|
/* 2DC */ VPABSD,
|
|
/* 2DD */ VPABSW,
|
|
/* 2DE */ VPACKSSDW,
|
|
/* 2DF */ VPACKSSWB,
|
|
/* 2E0 */ VPACKUSDW,
|
|
/* 2E1 */ VPACKUSWB,
|
|
/* 2E2 */ VPADDB,
|
|
/* 2E3 */ VPADDD,
|
|
/* 2E4 */ VPADDQ,
|
|
/* 2E5 */ VPADDSB,
|
|
/* 2E6 */ VPADDSW,
|
|
/* 2E7 */ VPADDUSB,
|
|
/* 2E8 */ VPADDUSW,
|
|
/* 2E9 */ VPADDW,
|
|
/* 2EA */ VPALIGNR,
|
|
/* 2EB */ VPAND,
|
|
/* 2EC */ VPANDN,
|
|
/* 2ED */ VPAVGB,
|
|
/* 2EE */ VPAVGW,
|
|
/* 2EF */ VPBLENDVB,
|
|
/* 2F0 */ VPBLENDW,
|
|
/* 2F1 */ VPCLMULQDQ,
|
|
/* 2F2 */ VPCMPEQB,
|
|
/* 2F3 */ VPCMPEQD,
|
|
/* 2F4 */ VPCMPEQQ,
|
|
/* 2F5 */ VPCMPEQW,
|
|
/* 2F6 */ VPCMPESTRI,
|
|
/* 2F7 */ VPCMPESTRM,
|
|
/* 2F8 */ VPCMPGTB,
|
|
/* 2F9 */ VPCMPGTD,
|
|
/* 2FA */ VPCMPGTQ,
|
|
/* 2FB */ VPCMPGTW,
|
|
/* 2FC */ VPCMPISTRI,
|
|
/* 2FD */ VPCMPISTRM,
|
|
/* 2FE */ VPERM2F128,
|
|
/* 2FF */ VPERMILPD,
|
|
/* 300 */ VPERMILPS,
|
|
/* 301 */ VPEXTRB,
|
|
/* 302 */ VPEXTRD,
|
|
/* 303 */ VPEXTRQ,
|
|
/* 304 */ VPEXTRW,
|
|
/* 305 */ VPHADDD,
|
|
/* 306 */ VPHADDSW,
|
|
/* 307 */ VPHADDW,
|
|
/* 308 */ VPHMINPOSUW,
|
|
/* 309 */ VPHSUBD,
|
|
/* 30A */ VPHSUBSW,
|
|
/* 30B */ VPHSUBW,
|
|
/* 30C */ VPINSRB,
|
|
/* 30D */ VPINSRD,
|
|
/* 30E */ VPINSRQ,
|
|
/* 30F */ VPINSRW,
|
|
/* 310 */ VPMADDUBSW,
|
|
/* 311 */ VPMADDWD,
|
|
/* 312 */ VPMAXSB,
|
|
/* 313 */ VPMAXSD,
|
|
/* 314 */ VPMAXSW,
|
|
/* 315 */ VPMAXUB,
|
|
/* 316 */ VPMAXUD,
|
|
/* 317 */ VPMAXUW,
|
|
/* 318 */ VPMINSB,
|
|
/* 319 */ VPMINSD,
|
|
/* 31A */ VPMINSW,
|
|
/* 31B */ VPMINUB,
|
|
/* 31C */ VPMINUD,
|
|
/* 31D */ VPMINUW,
|
|
/* 31E */ VPMOVMSKB,
|
|
/* 31F */ VPMOVSXBD,
|
|
/* 320 */ VPMOVSXBQ,
|
|
/* 321 */ VPMOVSXBW,
|
|
/* 322 */ VPMOVSXWD,
|
|
/* 323 */ VPMOVSXWQ,
|
|
/* 324 */ VPMOVZXBD,
|
|
/* 325 */ VPMOVZXBQ,
|
|
/* 326 */ VPMOVZXBW,
|
|
/* 327 */ VPMOVZXDQ,
|
|
/* 328 */ VPMOVZXWD,
|
|
/* 329 */ VPMOVZXWQ,
|
|
/* 32A */ VPMULDQ,
|
|
/* 32B */ VPMULHRSW,
|
|
/* 32C */ VPMULHUW,
|
|
/* 32D */ VPMULHW,
|
|
/* 32E */ VPMULLD,
|
|
/* 32F */ VPMULLW,
|
|
/* 330 */ VPOR,
|
|
/* 331 */ VPSADBW,
|
|
/* 332 */ VPSHUFB,
|
|
/* 333 */ VPSHUFD,
|
|
/* 334 */ VPSHUFHW,
|
|
/* 335 */ VPSHUFLW,
|
|
/* 336 */ VPSIGNB,
|
|
/* 337 */ VPSIGND,
|
|
/* 338 */ VPSIGNW,
|
|
/* 339 */ VPSLLD,
|
|
/* 33A */ VPSLLDQ,
|
|
/* 33B */ VPSLLQ,
|
|
/* 33C */ VPSLLW,
|
|
/* 33D */ VPSRAD,
|
|
/* 33E */ VPSRAW,
|
|
/* 33F */ VPSRLD,
|
|
/* 340 */ VPSRLDQ,
|
|
/* 341 */ VPSRLQ,
|
|
/* 342 */ VPSRLW,
|
|
/* 343 */ VPSUBB,
|
|
/* 344 */ VPSUBD,
|
|
/* 345 */ VPSUBQ,
|
|
/* 346 */ VPSUBSB,
|
|
/* 347 */ VPSUBSW,
|
|
/* 348 */ VPSUBUSB,
|
|
/* 349 */ VPSUBUSW,
|
|
/* 34A */ VPSUBW,
|
|
/* 34B */ VPTEST,
|
|
/* 34C */ VPUNPCKHBW,
|
|
/* 34D */ VPUNPCKHDQ,
|
|
/* 34E */ VPUNPCKHQDQ,
|
|
/* 34F */ VPUNPCKHWD,
|
|
/* 350 */ VPUNPCKLBW,
|
|
/* 351 */ VPUNPCKLDQ,
|
|
/* 352 */ VPUNPCKLQDQ,
|
|
/* 353 */ VPUNPCKLWD,
|
|
/* 354 */ VPXOR,
|
|
/* 355 */ VRCPPS,
|
|
/* 356 */ VRCPSS,
|
|
/* 357 */ VROUNDPD,
|
|
/* 358 */ VROUNDPS,
|
|
/* 359 */ VROUNDSD,
|
|
/* 35A */ VROUNDSS,
|
|
/* 35B */ VRSQRTPS,
|
|
/* 35C */ VRSQRTSS,
|
|
/* 35D */ VSHUFPD,
|
|
/* 35E */ VSHUFPS,
|
|
/* 35F */ VSQRTPD,
|
|
/* 360 */ VSQRTPS,
|
|
/* 361 */ VSQRTSD,
|
|
/* 362 */ VSQRTSS,
|
|
/* 363 */ VSTMXCSR,
|
|
/* 364 */ VSUBPD,
|
|
/* 365 */ VSUBPS,
|
|
/* 366 */ VSUBSD,
|
|
/* 367 */ VSUBSS,
|
|
/* 368 */ VTESTPD,
|
|
/* 369 */ VTESTPS,
|
|
/* 36A */ VUCOMISD,
|
|
/* 36B */ VUCOMISS,
|
|
/* 36C */ VUNPCKHPD,
|
|
/* 36D */ VUNPCKHPS,
|
|
/* 36E */ VUNPCKLPD,
|
|
/* 36F */ VUNPCKLPS,
|
|
/* 370 */ VXORPD,
|
|
/* 371 */ VXORPS,
|
|
/* 372 */ VZEROALL,
|
|
/* 373 */ VZEROUPPER,
|
|
/* 374 */ WAIT,
|
|
/* 375 */ WBINVD,
|
|
/* 376 */ WRMSR,
|
|
/* 377 */ XADD,
|
|
/* 378 */ XCHG,
|
|
/* 379 */ XCRYPTCBC,
|
|
/* 37A */ XCRYPTCFB,
|
|
/* 37B */ XCRYPTCTR,
|
|
/* 37C */ XCRYPTECB,
|
|
/* 37D */ XCRYPTOFB,
|
|
/* 37E */ XGETBV,
|
|
/* 37F */ XLATB,
|
|
/* 380 */ XOR,
|
|
/* 381 */ XORPD,
|
|
/* 382 */ XORPS,
|
|
/* 383 */ XRSTOR,
|
|
/* 384 */ XSAVE,
|
|
/* 385 */ XSETBV,
|
|
/* 386 */ XSHA1,
|
|
/* 387 */ XSHA256,
|
|
/* 388 */ XSTORE,
|
|
};
|
|
|
|
/**
|
|
* @brief Defines an alias representing an opcode tree node. An opcode tree node is a 16 bit
|
|
* unsigned integer value with its first 4 bits reserved for the node type.
|
|
*/
|
|
typedef uint16_t OpcodeTreeNode;
|
|
|
|
/**
|
|
* @brief Values that represent the type of an opcode tree node.
|
|
*/
|
|
enum class OpcodeTreeNodeType : uint8_t
|
|
{
|
|
/**
|
|
* @brief Reference to a concrete instruction definition.
|
|
*/
|
|
INSTRUCTION_DEFINITION = 0,
|
|
/**
|
|
* @brief Reference to an opcode table.
|
|
*/
|
|
TABLE = 1,
|
|
/**
|
|
* @brief Reference to a modrm_mod switch table.
|
|
*/
|
|
MODRM_MOD = 2,
|
|
/**
|
|
* @brief Reference to a modrm_reg switch table.
|
|
*/
|
|
MODRM_REG = 3,
|
|
/**
|
|
* @brief Reference to a modrm_rm switch table.
|
|
*/
|
|
MODRM_RM = 4,
|
|
/**
|
|
* @brief Reference to a mandatory-prefix switch table.
|
|
*/
|
|
MANDATORY = 5,
|
|
/**
|
|
* @brief Reference to a x87 opcode table.
|
|
*/
|
|
X87 = 6,
|
|
/**
|
|
* @brief Reference to an address-size switch table.
|
|
*/
|
|
ADDRESS_SIZE = 7,
|
|
/**
|
|
* @brief Reference to an operand-size switch table.
|
|
*/
|
|
OPERAND_SIZE = 8,
|
|
/**
|
|
* @brief Reference to a cpu-mode switch table.
|
|
*/
|
|
MODE = 9,
|
|
/**
|
|
* @brief Reference to a vendor switch table.
|
|
*/
|
|
VENDOR = 10,
|
|
/**
|
|
* @brief Reference to a 3dnow! opcode table.
|
|
*/
|
|
AMD3DNOW = 11,
|
|
/**
|
|
* @brief Reference to a vex-prefix switch table.
|
|
*/
|
|
VEX = 12,
|
|
/**
|
|
* @brief Reference to a vex_w switch table.
|
|
*/
|
|
VEXW = 13,
|
|
/**
|
|
* @brief Reference to a vex_l switch table.
|
|
*/
|
|
VEXL = 14
|
|
};
|
|
|
|
/**
|
|
* @brief Values that represent the type of an operand in the instruction definition.
|
|
*/
|
|
enum class DefinedOperandType : uint8_t
|
|
{
|
|
/*
|
|
* @brief No operand.
|
|
*/
|
|
NONE,
|
|
/*
|
|
* @brief Direct address. The instruction has no ModR/M byte; the address of the operand is
|
|
* encoded in the instruction; no base register, index register, or scaling factor
|
|
* can be applied.
|
|
*/
|
|
A,
|
|
/*
|
|
* @brief The reg field of the ModR/M byte selects a control register.
|
|
*/
|
|
C,
|
|
/*
|
|
* @brief The reg field of the ModR/M byte selects a debug register.
|
|
*/
|
|
D,
|
|
/*
|
|
* @brief A ModR/M byte follows the opcode and specifies the operand. The operand is either
|
|
* a general-purpose register or a memory address. If it is a memory address, the
|
|
* address is computed from a segment register and any of the following values:
|
|
* a base register, an index register, a scaling factor, or a displacement.
|
|
*/
|
|
E,
|
|
/*
|
|
* @brief rFLAGS register.
|
|
*/
|
|
F,
|
|
/*
|
|
* @brief The reg field of the ModR/M byte selects a general register.
|
|
*/
|
|
G,
|
|
/*
|
|
* @brief The r/m field of the ModR/M byte always selects a general register, regardless of
|
|
* the mod field.
|
|
*/
|
|
H,
|
|
/*
|
|
* @brief Immediate data. The operand value is encoded in subsequent bytes of the
|
|
* instruction.
|
|
*/
|
|
I,
|
|
/*
|
|
* @brief Signed immediate data. The operand value is encoded in subsequent bytes of the
|
|
* instruction.
|
|
*/
|
|
sI,
|
|
/*
|
|
* @brief Constant immediate data value of 1.
|
|
*/
|
|
I1,
|
|
/*
|
|
* @brief The instruction contains a relative offset to be added to the instruction pointer
|
|
* register.
|
|
*/
|
|
J,
|
|
/*
|
|
* @brief Source operand is encoded in immediate byte (VEX only).
|
|
*/
|
|
L,
|
|
/*
|
|
* @brief The ModR/M byte may refer only to memory: mod != 11bin.
|
|
*/
|
|
M,
|
|
/*
|
|
* @brief Combination of M and R.
|
|
*/
|
|
MR,
|
|
/*
|
|
* @brief Combination of M and U.
|
|
*/
|
|
MU,
|
|
/*
|
|
* @brief The R/M field of the ModR/M byte selects a packed quadword MMX technology register.
|
|
*/
|
|
N,
|
|
/*
|
|
* @brief The instruction has no ModR/M byte; the offset of the operand is coded as a word,
|
|
* double word or quad word (depending on address size attribute) in the instruction.
|
|
* No base register, index register, or scaling factor can be applied.
|
|
*/
|
|
O,
|
|
/*
|
|
* @brief The reg field of the ModR/M byte selects a packed quadword MMX technology register.
|
|
*/
|
|
P,
|
|
/*
|
|
* @brief A ModR/M byte follows the opcode and specifies the operand. The operand is either
|
|
* an MMX technology register or a memory address. If it is a memory address, the
|
|
* address is computed from a segment register and any of the following values:
|
|
* a base register, an index register, a scaling factor, and a displacement.
|
|
*/
|
|
Q,
|
|
/*
|
|
* @brief The mod field of the ModR/M byte may refer only to a general register.
|
|
*/
|
|
R,
|
|
/*
|
|
* @brief The reg field of the ModR/M byte selects a segment register.
|
|
*/
|
|
S,
|
|
/*
|
|
* @brief The R/M field of the ModR/M byte selects a 128-bit XMM register.
|
|
*/
|
|
U,
|
|
/*
|
|
* @brief The reg field of the ModR/M byte selects a 128-bit XMM register.
|
|
*/
|
|
V,
|
|
/*
|
|
* @brief A ModR/M byte follows the opcode and specifies the operand. The operand is either
|
|
* a 128-bit XMM register or a memory address. If it is a memory address, the address
|
|
* is computed from a segment register and any of the following values:
|
|
* a base register, an index register, a scaling factor, and a displacement.
|
|
*/
|
|
W,
|
|
/**
|
|
* @brief Register 0.
|
|
*/
|
|
R0,
|
|
/**
|
|
* @brief Register 1.
|
|
*/
|
|
R1,
|
|
/**
|
|
* @brief Register 2.
|
|
*/
|
|
R2,
|
|
/**
|
|
* @brief Register 3.
|
|
*/
|
|
R3,
|
|
/**
|
|
* @brief Register 4.
|
|
*/
|
|
R4,
|
|
/**
|
|
* @brief Register 5.
|
|
*/
|
|
R5,
|
|
/**
|
|
* @brief Register 6.
|
|
*/
|
|
R6,
|
|
/**
|
|
* @brief Register 7.
|
|
*/
|
|
R7,
|
|
/**
|
|
* @brief AL register.
|
|
*/
|
|
AL,
|
|
/**
|
|
* @brief CL register.
|
|
*/
|
|
CL,
|
|
/**
|
|
* @brief DL register.
|
|
*/
|
|
DL,
|
|
/**
|
|
* @brief AX register.
|
|
*/
|
|
AX,
|
|
/**
|
|
* @brief CX register.
|
|
*/
|
|
CX,
|
|
/**
|
|
* @brief DX register.
|
|
*/
|
|
DX,
|
|
/**
|
|
* @brief EAX register.
|
|
*/
|
|
EAX,
|
|
/**
|
|
* @brief ECX register.
|
|
*/
|
|
ECX,
|
|
/**
|
|
* @brief EDX register.
|
|
*/
|
|
EDX,
|
|
/**
|
|
* @brief RAX register.
|
|
*/
|
|
RAX,
|
|
/**
|
|
* @brief RCX register.
|
|
*/
|
|
RCX,
|
|
/**
|
|
* @brief RDX register.
|
|
*/
|
|
RDX,
|
|
/**
|
|
* @brief ES segment register.
|
|
*/
|
|
ES,
|
|
/**
|
|
* @brief CS segment register.
|
|
*/
|
|
CS,
|
|
/**
|
|
* @brief SS segment register.
|
|
*/
|
|
SS,
|
|
/**
|
|
* @brief DS segment register.
|
|
*/
|
|
DS,
|
|
/**
|
|
* @brief FS segment register.
|
|
*/
|
|
FS,
|
|
/**
|
|
* @brief GS segment register.
|
|
*/
|
|
GS,
|
|
/**
|
|
* @brief Floating point register 0.
|
|
*/
|
|
ST0,
|
|
/**
|
|
* @brief Floating point register 1.
|
|
*/
|
|
ST1,
|
|
/**
|
|
* @brief Floating point register 2.
|
|
*/
|
|
ST2,
|
|
/**
|
|
* @brief Floating point register 3.
|
|
*/
|
|
ST3,
|
|
/**
|
|
* @brief Floating point register 4.
|
|
*/
|
|
ST4,
|
|
/**
|
|
* @brief Floating point register 5.
|
|
*/
|
|
ST5,
|
|
/**
|
|
* @brief Floating point register 6.
|
|
*/
|
|
ST6,
|
|
/**
|
|
* @brief Floating point register 7.
|
|
*/
|
|
ST7
|
|
};
|
|
|
|
/**
|
|
* @brief Values that represent the size of an operand in the instruction definition.
|
|
* Do not change the order or the values of this enum!
|
|
*/
|
|
enum class DefinedOperandSize : uint8_t
|
|
{
|
|
/**
|
|
* @brief No operand.
|
|
*/
|
|
NA = 0,
|
|
/**
|
|
* @brief Word, dword or qword.
|
|
*/
|
|
Z,
|
|
/**
|
|
* @brief Word, dword or qword.
|
|
*/
|
|
V,
|
|
/**
|
|
* @brief Dword or qword.
|
|
*/
|
|
Y,
|
|
/**
|
|
* @brief Oword or yword.
|
|
*/
|
|
X,
|
|
/**
|
|
* @brief Dword or qword, depending on the disassembler mode.
|
|
*/
|
|
RDQ,
|
|
/*
|
|
* @brief Byte, regardless of operand-size attribute.
|
|
*/
|
|
B,
|
|
/*
|
|
* @brief Word, regardless of operand-size attribute.
|
|
*/
|
|
W,
|
|
/*
|
|
* @brief Doubleword, regardless of operand-size attribute.
|
|
*/
|
|
D,
|
|
/*
|
|
* @brief Quadword, regardless of operand-size attribute.
|
|
*/
|
|
Q,
|
|
/*
|
|
* @brief 10-byte far pointer.
|
|
*/
|
|
T,
|
|
/**
|
|
* @brief TODO:
|
|
*/
|
|
O,
|
|
/*
|
|
* @brief Double-quadword, regardless of operand-size attribute.
|
|
*/
|
|
DQ,
|
|
/*
|
|
* @brief Quad-quadword, regardless of operand-size attribute.
|
|
*/
|
|
QQ,
|
|
/**
|
|
* @brief B sized register or D sized memory operand.
|
|
*/
|
|
BD = (static_cast<uint8_t>(B) << 4) | static_cast<uint8_t>(D),
|
|
/**
|
|
* @brief B sized register or V sized memory operand.
|
|
*/
|
|
BV = (static_cast<uint8_t>(B) << 4) | static_cast<uint8_t>(V),
|
|
/**
|
|
* @brief W sized register or D sized memory operand.
|
|
*/
|
|
WD = (static_cast<uint8_t>(W) << 4) | static_cast<uint8_t>(D),
|
|
/**
|
|
* @brief W sized register or V sized memory operand.
|
|
*/
|
|
WV = (static_cast<uint8_t>(W) << 4) | static_cast<uint8_t>(V),
|
|
/**
|
|
* @brief W sized register or Y sized memory operand.
|
|
*/
|
|
WY = (static_cast<uint8_t>(W) << 4) | static_cast<uint8_t>(Y),
|
|
/**
|
|
* @brief D sized register or Y sized memory operand.
|
|
*/
|
|
DY = (static_cast<uint8_t>(D) << 4) | static_cast<uint8_t>(Y),
|
|
/**
|
|
* @brief W sized register or O sized memory operand.
|
|
*/
|
|
WO = (static_cast<uint8_t>(W) << 4) | static_cast<uint8_t>(O),
|
|
/**
|
|
* @brief D sized register or O sized memory operand.
|
|
*/
|
|
DO = (static_cast<uint8_t>(D) << 4) | static_cast<uint8_t>(O),
|
|
/**
|
|
* @brief Q sized register or O sized memory operand.
|
|
*/
|
|
QO = (static_cast<uint8_t>(Q) << 4) | static_cast<uint8_t>(O),
|
|
};
|
|
|
|
/**
|
|
* @brief Values that represent optional flags in the instruction definition.
|
|
* Do not change the order or the values of this enum!
|
|
*/
|
|
enum InstructionDefinitionFlags : uint16_t
|
|
{
|
|
/**
|
|
* @brief The instruction accepts the rex.b prefix value.
|
|
*/
|
|
IDF_ACCEPTS_REXB = 0x0001,
|
|
/**
|
|
* @brief The instruction accepts the rex.x prefix value.
|
|
*/
|
|
IDF_ACCEPTS_REXX = 0x0002,
|
|
/**
|
|
* @brief The instruction accepts the rex.r prefix value.
|
|
*/
|
|
IDF_ACCEPTS_REXR = 0x0004,
|
|
/**
|
|
* @brief The instruction accepts the rex.w prefix value.
|
|
*/
|
|
IDF_ACCEPTS_REXW = 0x0008,
|
|
/**
|
|
* @brief The instruction accepts the address size override prefix (0x67).
|
|
*/
|
|
IDF_ACCEPTS_ADDRESS_SIZE_PREFIX = 0x0010,
|
|
/**
|
|
* @brief The instruction accepts the operand size override prefix (0x66).
|
|
*/
|
|
IDF_ACCEPTS_OPERAND_SIZE_PREFIX = 0x0020,
|
|
/**
|
|
* @brief The instruction accepts the segment override prefix.
|
|
*/
|
|
IDF_ACCEPTS_SEGMENT_PREFIX = 0x0040,
|
|
/**
|
|
* @brief The instruction accepts the REP prefix.
|
|
*/
|
|
IDF_ACCEPTS_REP_PREFIX = 0x0080,
|
|
/**
|
|
* @brief The instruction accepts the vex.l prefix value.
|
|
*/
|
|
IDF_ACCEPTS_VEXL = 0x0100,
|
|
/**
|
|
* @brief The instruction is invalid in 64 bit mode.
|
|
*/
|
|
IDF_INVALID_64 = 0x0200,
|
|
/**
|
|
* @brief The instructions operand size defaults to quadword in 64 bit mode.
|
|
*/
|
|
IDF_DEFAULT_64 = 0x0400,
|
|
/**
|
|
* @brief The first operand of the instruction is accessed in write mode.
|
|
*/
|
|
IDF_OPERAND1_WRITE = 0x0800,
|
|
/**
|
|
* @brief The first operand of the instruction is accessed in read-write mode.
|
|
*/
|
|
IDF_OPERAND1_READWRITE = 0x1000,
|
|
/**
|
|
* @brief The second operand of the instruction is accessed in write mode.
|
|
*/
|
|
IDF_OPERAND2_WRITE = 0x2000,
|
|
/**
|
|
* @brief The second operand of the instruction is accessed in read-write mode.
|
|
*/
|
|
IDF_OPERAND2_READWRITE = 0x4000
|
|
};
|
|
|
|
#pragma pack (push, 1)
|
|
/**
|
|
* @brief An operand definition.
|
|
*/
|
|
struct OperandDefinition
|
|
{
|
|
/**
|
|
* @brief The defined operand type.
|
|
*/
|
|
DefinedOperandType type;
|
|
/**
|
|
* @brief The defined operand size.
|
|
*/
|
|
DefinedOperandSize size;
|
|
};
|
|
/**
|
|
* @brief An instruction definition.
|
|
*/
|
|
struct InstructionDefinition
|
|
{
|
|
/**
|
|
* @brief The instruction mnemonic.
|
|
*/
|
|
InstructionMnemonic mnemonic;
|
|
/**
|
|
* @brief The operand definitions for all four possible operands.
|
|
*/
|
|
OperandDefinition operand[4];
|
|
/**
|
|
* @brief Additional flags for the instruction definition.
|
|
*/
|
|
uint16_t flags;
|
|
};
|
|
#pragma pack (pop)
|
|
|
|
namespace Internal
|
|
{
|
|
|
|
/**
|
|
* @brief Contains all opcode tables.
|
|
* Indexed by the numeric value of the opcode.
|
|
*/
|
|
extern const OpcodeTreeNode optreeTable[][256];
|
|
/**
|
|
* @brief Contains all modrm_mod switch tables.
|
|
* Index values:
|
|
* 0 = [modrm_mod == !11]
|
|
* 1 = [modrm_mod == 11]
|
|
*/
|
|
extern const OpcodeTreeNode optreeModrmMod[][2];
|
|
/**
|
|
* @brief Contains all modrm_reg switch tables.
|
|
* Indexed by the numeric value of the modrm_reg field.
|
|
*/
|
|
extern const OpcodeTreeNode optreeModrmReg[][8];
|
|
/**
|
|
* @brief Contains all modrm_rm switch tables.
|
|
* Indexed by the numeric value of the modrm_rm field.
|
|
*/
|
|
extern const OpcodeTreeNode optreeModrmRm[][8];
|
|
/**
|
|
* @brief Contains all mandatory-prefix switch tables.
|
|
* Index values:
|
|
* 0 = none
|
|
* 1 = F2
|
|
* 2 = F3
|
|
* 3 = 66
|
|
*/
|
|
extern const OpcodeTreeNode optreeMandatory[][4];
|
|
/**
|
|
* @brief Contains all x87 opcode tables.
|
|
* Indexed by the numeric value of the 6 lowest bits of the modrm byte (modrm_mod should
|
|
* always be 11).
|
|
*/
|
|
extern const OpcodeTreeNode optreeX87[][64];
|
|
/**
|
|
* @brief Contains all address-size switch tables.
|
|
* Index values:
|
|
* 0 = 16
|
|
* 1 = 32
|
|
* 2 = 64
|
|
*/
|
|
extern const OpcodeTreeNode optreeAddressSize[][3];
|
|
/**
|
|
* @brief Contains all operand-size switch tables.
|
|
* Index values:
|
|
* 0 = 16
|
|
* 1 = 32
|
|
* 2 = 64
|
|
*/
|
|
extern const OpcodeTreeNode optreeOperandSize[][3];
|
|
/**
|
|
* @brief Contains all cpu-mode switch tables.
|
|
* Index values:
|
|
* 0 = [!= 64]
|
|
* 1 = 64
|
|
*/
|
|
extern const OpcodeTreeNode optreeMode[][2];
|
|
/**
|
|
* @brief Contains all vendor switch tables.
|
|
* Index values:
|
|
* 0 = AMD
|
|
* 1 = Intel
|
|
*/
|
|
extern const OpcodeTreeNode optreeVendor[][2];
|
|
/**
|
|
* @brief Contains all 3dnow! switch tables.
|
|
* Indexed by the numeric value of the 3dnow! opcode.
|
|
*/
|
|
extern const OpcodeTreeNode optree3dnow[][256];
|
|
/**
|
|
* @brief Contains all vex switch tables.
|
|
* Index values:
|
|
* 0 = none
|
|
* 1 = 0F
|
|
* 2 = 0F38
|
|
* 3 = 0F3A
|
|
* 4 = 66
|
|
* 5 = 66_0F
|
|
* 6 = 66_0F38
|
|
* 7 = 66_0F3A
|
|
* 8 = F3
|
|
* 9 = F3_0F
|
|
* A = F3_0F38
|
|
* B = F3_0F3A
|
|
* C = F2
|
|
* D = F2_0F
|
|
* E = F2_0F38
|
|
* F = F2_0F3A
|
|
*/
|
|
extern const OpcodeTreeNode optreeVex[][16];
|
|
/**
|
|
* @brief Contains all vex_w switch tables.
|
|
* Indexed by the numeric value of the vex_w field.
|
|
*/
|
|
extern const OpcodeTreeNode optreeVexW[][2];
|
|
/**
|
|
* @brief Contains all vex_l switch tables.
|
|
* Indexed by the numeric value of the vex_l field.
|
|
*/
|
|
extern const OpcodeTreeNode optreeVexL[][2];
|
|
/**
|
|
* @brief Contains all instruction definitions.
|
|
*/
|
|
extern const InstructionDefinition instrDefinitions[];
|
|
/**
|
|
* @brief Contains all instruction mnemonic strings.
|
|
*/
|
|
extern const char* instrMnemonicStrings[];
|
|
|
|
/**
|
|
* @brief Returns the type of the specified opcode tree node.
|
|
* @param node The node.
|
|
* @return The type of the specified opcode tree node.
|
|
*/
|
|
inline OpcodeTreeNodeType GetOpcodeNodeType(OpcodeTreeNode node)
|
|
{
|
|
return static_cast<OpcodeTreeNodeType>((node >> 12) & 0x0F);
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the value of the specified opcode tree node.
|
|
* @param node The node.
|
|
* @return The value of the specified opcode tree node.
|
|
*/
|
|
inline uint16_t GetOpcodeNodeValue(OpcodeTreeNode node)
|
|
{
|
|
return (node & 0x0FFF);
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the root node of the opcode tree.
|
|
* @return The root node of the opcode tree.
|
|
*/
|
|
inline OpcodeTreeNode GetOpcodeTreeRoot()
|
|
{
|
|
return 0x1000;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns a child node of @c parent specified by @c index.
|
|
* @param parent The parent node.
|
|
* @param index The index of the child node to retrieve.
|
|
* @return The specified child node.
|
|
*/
|
|
inline OpcodeTreeNode GetOpcodeTreeChild(OpcodeTreeNode parent, uint16_t index)
|
|
{
|
|
using namespace Internal;
|
|
OpcodeTreeNodeType nodeType = GetOpcodeNodeType(parent);
|
|
uint16_t tableIndex = GetOpcodeNodeValue(parent);
|
|
switch (nodeType)
|
|
{
|
|
case OpcodeTreeNodeType::TABLE:
|
|
assert(index < 256);
|
|
return optreeTable[tableIndex][index];
|
|
case OpcodeTreeNodeType::MODRM_MOD:
|
|
assert(index < 2);
|
|
return optreeModrmMod[tableIndex][index];
|
|
case OpcodeTreeNodeType::MODRM_REG:
|
|
assert(index < 8);
|
|
return optreeModrmReg[tableIndex][index];
|
|
case OpcodeTreeNodeType::MODRM_RM:
|
|
assert(index < 8);
|
|
return optreeModrmRm[tableIndex][index];
|
|
case OpcodeTreeNodeType::MANDATORY:
|
|
assert(index < 4);
|
|
return optreeMandatory[tableIndex][index];
|
|
case OpcodeTreeNodeType::X87:
|
|
assert(index < 64);
|
|
return optreeX87[tableIndex][index];
|
|
case OpcodeTreeNodeType::ADDRESS_SIZE:
|
|
assert(index < 3);
|
|
return optreeAddressSize[tableIndex][index];
|
|
case OpcodeTreeNodeType::OPERAND_SIZE:
|
|
assert(index < 3);
|
|
return optreeOperandSize[tableIndex][index];
|
|
case OpcodeTreeNodeType::MODE:
|
|
assert(index < 2);
|
|
return optreeMode[tableIndex][index];
|
|
case OpcodeTreeNodeType::VENDOR:
|
|
assert(index < 3);
|
|
return optreeVendor[tableIndex][index];
|
|
case OpcodeTreeNodeType::AMD3DNOW:
|
|
assert(index < 256);
|
|
return optree3dnow[tableIndex][index];
|
|
case OpcodeTreeNodeType::VEX:
|
|
assert(index < 16);
|
|
return optreeVex[tableIndex][index];
|
|
case OpcodeTreeNodeType::VEXW:
|
|
assert(index < 2);
|
|
return optreeVexW[tableIndex][index];
|
|
case OpcodeTreeNodeType::VEXL:
|
|
assert(index < 2);
|
|
return optreeVexL[tableIndex][index];
|
|
default:
|
|
assert(0);
|
|
}
|
|
return 0xFFFF;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the instruction definition that is linked to the given @c node.
|
|
* @param node The instruction definition node.
|
|
* @return Pointer to the instruction definition.
|
|
*/
|
|
inline const InstructionDefinition* GetInstructionDefinition(OpcodeTreeNode node)
|
|
{
|
|
assert(GetOpcodeNodeType(node) == OpcodeTreeNodeType::INSTRUCTION_DEFINITION);
|
|
return& instrDefinitions[node & 0x0FFF];
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the specified instruction mnemonic string.
|
|
* @param mnemonic The mnemonic.
|
|
* @return The instruction mnemonic string.
|
|
*/
|
|
inline const char* GetInstructionMnemonicString(InstructionMnemonic mnemonic)
|
|
{
|
|
return instrMnemonicStrings[static_cast<uint16_t>(mnemonic)];
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the numeric value for a simple operand size definition.
|
|
* @param operandSize The defined operand size.
|
|
* @return The the numeric value for the simple operand size definition.
|
|
*/
|
|
inline uint16_t GetSimpleOperandSize(DefinedOperandSize operandSize)
|
|
{
|
|
static uint16_t operandSizes[8] =
|
|
{
|
|
8, 16, 32, 64, 80, 12, 128, 256
|
|
};
|
|
uint16_t index =
|
|
static_cast<uint8_t>(operandSize) - static_cast<uint8_t>(DefinedOperandSize::B);
|
|
assert(index < 8);
|
|
return operandSizes[index];
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the memory-size part of a complex operand size definition.
|
|
* @param operandSize The defined operand size.
|
|
* @return The memory-size part of the operand size definition.
|
|
*/
|
|
inline DefinedOperandSize GetComplexOperandMemSize(DefinedOperandSize operandSize)
|
|
{
|
|
return static_cast<DefinedOperandSize>(static_cast<uint8_t>(operandSize) & 0x0F);
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the register-size part of a complex operand size definition.
|
|
* @param operandSize The defined operand size.
|
|
* @return The register-size part of the operand size definition.
|
|
*/
|
|
inline DefinedOperandSize GetComplexOperandRegSize(DefinedOperandSize operandSize)
|
|
{
|
|
return static_cast<DefinedOperandSize>((static_cast<uint8_t>(operandSize) >> 4) & 0x0F);
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* _ZYDIS_OPCODETABLE_HPP_ */
|