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zydis
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Code Releases Activity
434 Commits 3 Branches 1 Tag 8.5 MiB
Commit Graph

16 Commits

Author SHA1 Message Date
Joel Höner cf24ee010a Introduced custom integer types 2017-11-25 01:47:02 +01:00
flobernd bb1708daaf Preparations for the CPU-flag info feature 2017-07-11 18:51:54 +02:00
flobernd 9628fb8367 Fixed order of segment-registers 2017-06-21 03:03:13 +02:00
flobernd 95b685a29d Minor bugfixes 
- Fixed some VEX/EVEX/MVEX-prefix error conditions
- MASK register size is now 64-bit for EVEX- and 16-bit for MVEX-instructions
 2017-06-20 17:48:55 +02:00
flobernd ad35e81eee Added semantic element-information for operands 2017-06-16 23:19:57 +02:00
flobernd 1db4db9ec2 Added semantic decoding of implicit register operands 2017-06-16 03:25:39 +02:00
flobernd deff3b8e55 Fixed register encoding 2017-01-22 21:44:42 +01:00
flobernd 4b54158aa2 Minor bugfixes 2017-01-20 00:01:56 +01:00
flobernd 4165c3b9b2 Removed Input-struct. The input buffer is now directly passed to the ZydisDecodeInstruction function. 2017-01-11 11:20:24 +01:00
flobernd 5b63557f3c Fixed decoding of instructions with EVEX high-16 register specifiers (R', X, V') 2016-12-05 21:06:29 +01:00
flobernd d4dd176438 Refactorings and bugfixes 
- Added support for the BOUND prefix
- Added support for more detailed operand-actions (read, write, readwrite, cond. read, cond. write, read + cond. write, write + cond. read)
- Added operand-visibility info (explicit, implicit, hidden)
- Fixed some bugs in the prefix-decoding routines
- Removed stdbool.h dependency and introduced custom boolean-type for better portability
 2016-12-05 02:24:01 +01:00
flobernd 9a0b1da975 Added missing registers and CPUID feature-flags 2016-11-27 23:24:43 +01:00
flobernd be56ef937d Minor bugfixes and refactorings 2016-11-21 14:55:17 +01:00
flobernd 58c73b2885 Bugfixes and Support for some more registers 
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
 2016-11-14 02:10:59 +01:00
flobernd 3f09ffca69 Minor refactorings and further preparation for advanced features 2016-11-11 22:03:26 +01:00
flobernd 7c9a6db6af Initial version 2.0 release 2016-05-25 21:25:48 +02:00