x64dbg
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zydis
mirror of https://github.com/x64dbg/zydis
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Code Releases Activity
93 Commits 3 Branches 1 Tag 8.5 MiB
Commit Graph

10 Commits

Author SHA1 Message Date
flobernd be56ef937d Minor bugfixes and refactorings 2016-11-21 14:55:17 +01:00
flobernd c4dce1adb9 Added support for test-register operands (TR0..TR7) 
- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
 2016-11-14 03:39:17 +01:00
flobernd 58c73b2885 Bugfixes and Support for some more registers 
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
 2016-11-14 02:10:59 +01:00
flobernd 3f09ffca69 Minor refactorings and further preparation for advanced features 2016-11-11 22:03:26 +01:00
flobernd 4c911f91b9 Minor bugfixes and refactorings 
* Fixed some instruction Definitions
* Implemented a primitive diffing-mode to compare different versions of the instruction-database (InstructionEditor)
 2016-09-21 20:02:09 +02:00
flobernd 317976afbf Minor bugfixes 2016-09-13 20:24:14 +02:00
flobernd 72907c6845 Added support for instructions with 5 operands 
* optimized table structure to support instructions with 5 operands (vpermil2ps, vpermil2pd)
* updated InstructionEditor
 2016-09-13 05:26:55 +02:00
flobernd 54f2bc43ac Preparations for optional feature support 2016-08-23 15:58:40 +02:00
flobernd a6e76d81b4 Preparations for optional feature support 2016-08-23 15:57:38 +02:00
flobernd 7c9a6db6af Initial version 2.0 release 2016-05-25 21:25:48 +02:00