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zydis
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427 Commits 3 Branches 1 Tag 8.5 MiB
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427 Commits

Author SHA1 Message Date
flobernd b9cf56af4d Refactorings 2017-07-04 16:10:21 +02:00
flobernd bbf8b1193b Added performance test 2017-07-03 21:10:04 +02:00
flobernd 87c9155207 Refactorings 2017-07-03 17:36:03 +02:00
flobernd 6ce34bd141 Added error-condition for illegal LOCK-prefixes 2017-07-03 17:02:32 +02:00
Joel Höner 7ba6ea0596 Moved private headers to `src` directory 2017-07-03 04:16:38 +02:00
flobernd d12059e043 Fixed examples and tools 2017-07-03 03:58:25 +02:00
flobernd 66fe376f36 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-07-03 03:38:13 +02:00
Joel Höner 2eb915a90e Fixed project structure in VS 2017-07-03 03:37:56 +02:00
flobernd 8e36baa98b Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-07-03 03:24:40 +02:00
Joel Höner 449176b140 Added basic install rules to CMakeLists 2017-07-03 03:21:24 +02:00
flobernd 38c67d2a85 Refactorings 2017-07-03 03:14:01 +02:00
Joel Höner a0f54a45c3 Modernized CMakeLists 2017-07-02 08:40:41 +02:00
flobernd ad8e5ce6a9 Minor refactorings 2017-07-01 01:10:03 +02:00
flobernd 392c36c85f Fixed decoding of MASK register (again) 2017-06-29 21:12:22 +02:00
flobernd c2a531902c Fixed decoding of MASK register 2017-06-29 21:07:08 +02:00
flobernd 1fe1894362 Minor bugfixes 2017-06-29 20:54:36 +02:00
flobernd aca1ad1414 Minor bugfixes 2017-06-29 20:52:35 +02:00
flobernd d7c81e5104 Fixed operand-size of some special MVEX instructions 2017-06-29 20:40:48 +02:00
flobernd 2ee8332529 Fixed operand-action for MVEX-instructions with `READWRITE` operands 2017-06-29 20:06:44 +02:00
flobernd 8ef597970d Minor bugfixes 
- Fixed operand-action for MVEX instructions with mask-register
- Fixed decoding of MVEX instructions without swizzle/broadcast/convert functionality
 2017-06-29 19:44:01 +02:00
flobernd 65fe4a4e6c Improved instruction decoding 
- Decoding of EVEX/MVEX instructions without a NDS/NDD-operand encoded in `.vvvv` and without a VSIB-operand will now fail, if `.v'` is != 1b
- Added information about XACQUIRE, XRELEASE and BOUND prefixes to the instruction definitions
- Fixed immediate-decoding of the `vpermil2pd` / `vpermil2ps` instruction
 2017-06-29 18:09:42 +02:00
flobernd 73b02f6d12 Updated some instruction-definitions to allow segment-overrides for implicit-memory operands 2017-06-28 22:42:39 +02:00
flobernd 778b47c02f Minor bugfixes 
- Fixed segment register for implicit memory-operands
- Fixed decoding of `MOV CR, GPR`, `MOV GPR, CR`, `MOV DR, GPR` and `MOV GPR, DR`
 2017-06-28 22:18:12 +02:00
flobernd 05817fa8e7 Fixed register decoding for XOP and VEX instructions (again) 2017-06-28 20:50:32 +02:00
flobernd 808ccac372 Fixed register decoding for XOP and VEX instructions 2017-06-28 20:46:32 +02:00
flobernd b118637dae Cleaned up register-decoding code 2017-06-28 19:50:33 +02:00
flobernd 55400e9206 Improved decoding of XOP/VEX/EVEX/MVEX instructions 
Decoding of XOP/VEX/EVEX/MVEX instructions without a NDS register encoded in .vvvv will now fail, if the .vvvv value is != 1111b
 2017-06-27 04:14:17 +02:00
flobernd e7a7be70e9 Performance optimizations 2017-06-27 03:32:42 +02:00
flobernd 920d62d699 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 03:20:26 +02:00
flobernd a1551af657 Fixed decoding of operands with VSIB index-register 2017-06-26 03:12:18 +02:00
flobernd 99de0f3152 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:54:49 +02:00
flobernd e15279ed1f Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:02:00 +02:00
flobernd 0c38e08306 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2017-06-25 23:50:13 +02:00
flobernd 652b5afadb Fixed operand-action for EVEX/MVEX instructions with write-mask 2017-06-25 23:49:19 +02:00
flobernd 3b45ae2f1d Minor bugfixes 2017-06-25 23:29:42 +02:00
Joel Höner b442fa55b4 Fixed tools 2017-06-25 23:28:15 +02:00
flobernd 83699fe9d0 Minor bugfixes 2017-06-25 23:24:43 +02:00
flobernd 96a7197647 Fixed segment-register priority in 64-bit mode 2017-06-24 04:35:48 +02:00
flobernd 3a346b5e9d Fixed segment-register for XOP/VEX/EVEX/MVEX instructions 2017-06-24 03:29:35 +02:00
flobernd 7d77e0747f Minor improvements to the instruction-decoder 
- Set mask-mode to "merge" for all MVEX instructions
- Set operand-action of EVEX dest-operands to RCW, if a merge write-mask is specified
 2017-06-24 03:20:45 +02:00
flobernd e04adf2b8d Fixed semantic decoding of EIP/RIP-relative displacements 2017-06-24 03:02:03 +02:00
flobernd 83ea3bc2c8 Minor bugfixes 2017-06-24 02:48:14 +02:00
flobernd 39bdaeeeb9 Some changes to the instruction-formatter 2017-06-24 02:16:16 +02:00
flobernd f0d1ef9725 Added some missing instructions 2017-06-24 02:11:32 +02:00
flobernd 0957a57ab4 Fixed vector-length for EVEX instructions with fixed vector-length 2017-06-24 00:01:21 +02:00
flobernd b3d508850f Added information for VEX/EVEX/MVEX instructions with static broadcast-factor 2017-06-23 20:47:34 +02:00
flobernd cd3bf5586b Changed default element-count from 0 to 1 2017-06-23 04:26:21 +02:00
flobernd c8c3d29ba4 Added support for MVEX instructions with static broadcast factor 2017-06-23 03:35:12 +02:00
flobernd 2297c763cf Added compressed disp8 calculation for MVEX instructions with element-granularity 2017-06-23 01:40:19 +02:00
flobernd d8f3843f57 Added compressed disp8 calculation for MVEX instructions without swizzle/broadcast/convert functionality 2017-06-23 01:15:42 +02:00