flobernd
a1d58c9ee7
Replaced `ZYDIS_FORMATTER_HOOK_PRINT_OPERAND_SEPARATOR` by `ZYDIS_FORMATTER_HOOK_PRE_OPERAND`/`ZYDIS_FORMATTER_HOOK_POST_OPERAND`
2017-12-02 19:42:30 +01:00
th0rex
022a4e7423
Add hook for operand seperator to formatter
2017-12-02 18:29:16 +01:00
flobernd
930c4df970
Removed `ZydisDecodedInstruction.instrPointer`
...
The instruction-pointer was always pointing to the next instruction (which is inconsistent for branch instructions). We can't always tell IF an instruction is going to branch (for the conditional ones), so we decided to completely remove it.
You can always manually combine `instrAddress` and `length` to calculate this value.
2017-12-01 20:21:25 +01:00
flobernd
1cd788f751
Minor table fixes
2017-12-01 01:18:25 +01:00
Joel Höner
58ce3a3e7f
Removed forgotten stdint.h include
2017-11-30 08:03:34 +01:00
flobernd
beeaa0e279
Added additional check for invalid AVX-512 zero masks
2017-11-29 22:47:09 +01:00
flobernd
6d690a4893
Improved file-size reduction for builds without `ZYDIS_FEATURE_EVEX`/`ZYDIS_FEATURE_MVEX`
2017-11-27 13:42:24 +01:00
Joel Höner
a2cc8615ba
Various minor no-libc fixes
2017-11-27 00:06:09 +01:00
Joel Höner
56f47f4863
Added support for compiling on ARM target
2017-11-26 04:38:32 +01:00
flobernd
8c69dba9db
Added handling of the `ZYDIS_FEATURE_EVEX` and `ZYDIS_FEATURE_MVEX` CMake switches
...
Disabling these features will only prevent some code from beeing generated. Completely removing EVEX/MVEX from the data-tables using a compiler-define is not possible at the moment (you have to re-generate the tables, if you want to save a few more bytes).
2017-11-25 18:14:05 +01:00
flobernd
dd9d9134d4
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2017-11-25 16:30:10 +01:00
Joel Höner
c4f5af64d0
Added own `NULL`
2017-11-25 03:18:08 +01:00
flobernd
31ff30f763
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2017-11-25 02:32:27 +01:00
Joel Höner
cf24ee010a
Introduced custom integer types
2017-11-25 01:47:02 +01:00
Joel Höner
066e7f359d
Removed old feature check flags
2017-11-25 00:41:27 +01:00
flobernd
3f66d84a02
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2017-11-24 22:31:03 +01:00
Joel Höner
f1316c434e
Fixed `ZydisMemorySet` implementation
2017-11-24 20:32:52 +01:00
Joel Höner
df949a5eb0
Improved no-libc support
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- Added `ZYDIS_NO_LIBC` CMake switch
- When enabled, removes dependency on `memset`, `memcpy` and `strlen`
2017-11-24 19:25:48 +01:00
flobernd
e789d11af1
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2017-11-24 17:55:00 +01:00
Joel Höner
fb452e5b59
Inverted feature gate macros
2017-11-23 22:42:25 +01:00
flobernd
a3d1490daa
Fixed some instruction definitions
2017-11-17 01:35:56 +01:00
flobernd
0f30c1679b
`KNC` instructions are only valid in 64-bit mode
2017-11-17 01:26:54 +01:00
flobernd
4195e9b0b8
Some decoder and formatter improvements
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- Added `const` specifiers to some local variables
- Added KNC compatibility-mode (`ZYDIS_DECODER_MODE_KNC`) to improve decoding of ambiguous KNC/KNL+ mask-instructions
2017-11-16 22:18:20 +01:00
flobernd
e314c71db3
Added some undocumented `PREFETCH` instructions
2017-11-16 18:47:42 +01:00
flobernd
626d0bc238
Minor bugfixes
2017-11-14 07:33:15 +01:00
flobernd
df101d0fe0
Decoder improvements
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- Instructions which are only valid in protected-mode are now rejected, if `ZYDIS_MACHINE_MODE_REAL_16` is used
- The `scale` of memory-operands is now correctly set to `1` in 16-bit mode, if an index register was specified
2017-11-13 19:43:19 +01:00
flobernd
ac3a01bd57
Fixed operand-size of `MOV GPR, DR` and `MOV DR, GPR` instructions
2017-11-13 14:37:37 +01:00
flobernd
5c634f71ad
Added formatter properties to set a custom hex-prefix/suffix
2017-11-13 13:52:02 +01:00
flobernd
9ccc096232
Minor table-changes to mirror the latest changes of the XED datatables
2017-11-07 22:18:51 +01:00
flobernd
adbfb9cd66
Added formatter properties to control padding of hexadecimal values
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- Renamed `ZydisFormatterSetAttribute` to `ZydisFormatterSetProperty`
- Renamed some formatter enums
- Added `ZYDIS_FORMATTER_PROP_ADDR_PADDING`
- Added `ZYDIS_FORMATTER_PROP_DISP_PADDING`
- Added `ZYDIS_FORMATTER_PROP_IMM_PADDING`
2017-11-06 21:35:13 +01:00
Joel Höner
a227bd4bbe
Fixed `mode == 0` in `ZydisDecoderEnableMode`
2017-11-03 22:48:33 +01:00
flobernd
cbf06b1bf3
Minor interface changes
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- Reverted last change
- Removed `ZydisFormatterInitEx`
- Added `ZydisFormatterSetAttribute`
2017-11-03 02:24:02 +01:00
Joel Höner
3a38b9ceb5
Revert "Minor interface changes"
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This reverts commit 0ba5c95dac
.
2017-11-02 23:03:21 +01:00
flobernd
0ba5c95dac
Minor interface changes
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- Removed `ZydisDecoderEnableMode`
- Added `ZydisDecoderInitEx` with an additional `flags` parameter that can be used to specify a mask of decoder-modes
2017-11-02 17:03:12 +01:00
flobernd
97a3425e31
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2017-11-01 23:39:20 +01:00
flobernd
57f7ff8bcd
Implemented decoder-modes to support ISA-extensions that conflict with existing instructions
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- Added decoder-modes
- `ZYDIS_DECODER_MODE_MINIMAL`
- `ZYDIS_DECODER_MODE_AMD_BRANCHES`
- `ZYDIS_DECODER_MODE_MPX`
- `ZYDIS_DECODER_MODE_CET`
- `ZYDIS_DECODER_MODE_LZCNT`
- `ZYDIS_DECODER_MODE_TZCNT`
- Removed `ZydisDecoderInitEx` and the possibility to pass a decoder-granularity (use `ZYDIS_DECODER_MODE_MINIMAL` instead)
2017-11-01 23:39:10 +01:00
Joel Höner
22318a04dd
Minor decoder fixes
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- Cosmetic changes
- Check `instruction` argument for `NULL`
2017-10-27 03:07:33 +02:00
flobernd
5ed561a0fc
Fixed `bndldx` and `bndstx` not accepting segment-overrides
2017-10-27 03:02:36 +02:00
flobernd
20b98c4a70
Minor bugfixes
2017-10-26 20:16:37 +02:00
flobernd
566ebf8566
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2017-10-26 20:11:01 +02:00
flobernd
38df6e0d1e
Improved support for MPX instructions
2017-10-26 20:10:51 +02:00
Joel Höner
95338c59bc
Added previously forgotten const qualifiers
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- Also, fixed integer comparision warning in `ZydisPerfTest`
2017-10-24 17:21:09 +02:00
flobernd
4de4def535
Fixed some MVEX instructions
2017-10-20 16:16:57 +02:00
flobernd
dd4c793885
Fixed messed-up assert condition
2017-10-19 22:19:20 +02:00
flobernd
668db54b18
Added implicit operands for instructions with stack-operations
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- Implicit SP/ESP/RSP register-operand
- Implicit [SP/ESP/RSP] memory-operand
2017-10-19 22:11:23 +02:00
flobernd
219200eebe
Minor table fixes
2017-10-19 17:36:08 +02:00
flobernd
9871cb414c
Minor bugfixes
2017-10-19 15:13:09 +02:00
flobernd
9fc44085d2
Added new ISA-extensions
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- BITALG
- GFNI
- RDPID
- VAES
- VBMI2
- VNNI
- VPCLMULQDQ
2017-10-19 01:10:25 +02:00
flobernd
750808bea5
Fixed some MVEX instructions
2017-10-17 18:05:17 +02:00
Joel Höner
d2c6115f6f
Fixed two formatter issues
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- Unintentional fallthrough
- Assertion on 0-length append
2017-10-17 17:44:19 +02:00