5 Commits

Author	SHA1	Message	Date
flobernd	be56ef937d	Minor bugfixes and refactorings	2016-11-21 14:55:17 +01:00
flobernd	58c73b2885	Bugfixes and Support for some more registers ... Zydis: - Fixed operand-size of some instructions in 64-bit mode - Fixed operand decoding of the "movq MM, GPR" instruction - Added table-registers (GDRT, LDTR, IDTR, TR) - Added test-registers (TR0..TR7) - Added BNDCFG and BNDSTATUS registers - Added MXCR register InstructionEditor: - The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables - Fixed conflict indication for some operand type/encoding combinations - Added conflict indication for X86Flags	2016-11-14 02:10:59 +01:00
flobernd	3f09ffca69	Minor refactorings and further preparation for advanced features	2016-11-11 22:03:26 +01:00
flobernd	52dd9fac89	Fixed CMake file	2016-06-20 01:33:29 +02:00
flobernd	7c9a6db6af	Initial version 2.0 release	2016-05-25 21:25:48 +02:00