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zydis
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255 Commits 3 Branches 1 Tag 8.5 MiB
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39 Commits

Author SHA1 Message Date
flobernd 778b47c02f Minor bugfixes 
- Fixed segment register for implicit memory-operands
- Fixed decoding of `MOV CR, GPR`, `MOV GPR, CR`, `MOV DR, GPR` and `MOV GPR, DR`
 2017-06-28 22:18:12 +02:00
flobernd 55400e9206 Improved decoding of XOP/VEX/EVEX/MVEX instructions 
Decoding of XOP/VEX/EVEX/MVEX instructions without a NDS register encoded in .vvvv will now fail, if the .vvvv value is != 1111b
 2017-06-27 04:14:17 +02:00
flobernd 99de0f3152 Fixed operand-action for EVEX/MVEX instructions with write-mask (again) 2017-06-26 00:54:49 +02:00
flobernd 83699fe9d0 Minor bugfixes 2017-06-25 23:24:43 +02:00
flobernd f0d1ef9725 Added some missing instructions 2017-06-24 02:11:32 +02:00
flobernd b3d508850f Added information for VEX/EVEX/MVEX instructions with static broadcast-factor 2017-06-23 20:47:34 +02:00
flobernd c8c3d29ba4 Added support for MVEX instructions with static broadcast factor 2017-06-23 03:35:12 +02:00
flobernd 2297c763cf Added compressed disp8 calculation for MVEX instructions with element-granularity 2017-06-23 01:40:19 +02:00
flobernd d8f3843f57 Added compressed disp8 calculation for MVEX instructions without swizzle/broadcast/convert functionality 2017-06-23 01:15:42 +02:00
flobernd 6c370d29c9 Added support for some MVEX special-cases 2017-06-22 22:10:18 +02:00
flobernd 76f0bcf00d Improved semantic decoding of MVEX instructions 2017-06-22 19:14:27 +02:00
flobernd 5bd81b7f1c Fixed sign-extension of displacement values 2017-06-22 01:38:41 +02:00
flobernd 52e1b59702 Improved EVEX and MVEX encoding 
- Added some MASK related error-conditions
- Added functionality and mask-policy attributes to the MVEX instruction-definition struct
- Added MVEX specific error-condition
 2017-06-20 21:23:06 +02:00
flobernd 95b685a29d Minor bugfixes 
- Fixed some VEX/EVEX/MVEX-prefix error conditions
- MASK register size is now 64-bit for EVEX- and 16-bit for MVEX-instructions
 2017-06-20 17:48:55 +02:00
flobernd 4487d1b252 Fixed some operand-size related filter-tables 2017-06-20 01:33:07 +02:00
flobernd 0902068007 Fixed more EVEX tuple-types 2017-06-19 21:06:33 +02:00
flobernd ee97ae753c Fixed some EVEX tuple-types 2017-06-19 20:46:42 +02:00
flobernd 4bceac86c9 Various bugfixes 
- Fixed operand-size and element-count of AGEN operands
- Fixed decoding of 8-bit modrm.rm register-operands
- Fixed vector-length for EVEX instructions with rounding-semantics
 2017-06-19 20:19:21 +02:00
flobernd 2d2e1acf27 Added T1_4X tuple-type 2017-06-18 22:02:59 +02:00
flobernd 6caa68b674 Reimplemented decoding of 3DNOW instructions and improved EVEX decoding 2017-06-13 22:04:29 +02:00
flobernd 702f6b8d53 Reimplemented a basic version of semantic operand-decoding 2017-06-13 20:17:20 +02:00
flobernd 8740b1e50f Major changes to the instruction decoder 
- Decoupled semantic operand decoding (optional) from physical instruction decoding
- Several optimizations of the internal structures
- Further preparations for MVEX-support
 2017-06-12 19:16:01 +02:00
flobernd 3b56c867fc Updated mask-policy definitions for EVEX instructions 2017-01-11 22:11:30 +01:00
flobernd 5b63557f3c Fixed decoding of instructions with EVEX high-16 register specifiers (R', X, V') 2016-12-05 21:06:29 +01:00
flobernd d4dd176438 Refactorings and bugfixes 
- Added support for the BOUND prefix
- Added support for more detailed operand-actions (read, write, readwrite, cond. read, cond. write, read + cond. write, write + cond. read)
- Added operand-visibility info (explicit, implicit, hidden)
- Fixed some bugs in the prefix-decoding routines
- Removed stdbool.h dependency and introduced custom boolean-type for better portability
 2016-12-05 02:24:01 +01:00
flobernd bb913f1272 Fixed some instruction-definitions and re-generated tables 2016-11-29 23:48:10 +01:00
flobernd 816bb570c7 Complete rewrite of the instruction-formatter 
- Added hooking functionality to support custom instruction-formatting
- Added FormatterHooks demo that demonstrates the hooking functionality

InstructionEditor:
- Fixed issues with still non-deterministic output on code-generation
 2016-11-26 13:08:37 +01:00
flobernd 7f1c0bd8f1 Minor refactorings and bugfixes 2016-11-24 10:57:23 +01:00
flobernd 1159966784 Changed definition-sorting to produce deterministic output (JSON and generated tables) 2016-11-22 21:47:54 +01:00
flobernd 7f7cbd8dcd Internal changes and optimizations of the generated tables and the InstructionEditor 2016-11-22 18:12:05 +01:00
flobernd c4dce1adb9 Added support for test-register operands (TR0..TR7) 
- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
 2016-11-14 03:39:17 +01:00
flobernd f5610b937e Fixed code generation and tables (again) 2016-11-14 02:53:16 +01:00
flobernd ead586b722 Fixed code generation and tables 2016-11-14 02:22:29 +01:00
flobernd 58c73b2885 Bugfixes and Support for some more registers 
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
 2016-11-14 02:10:59 +01:00
flobernd 98e9559d6d Fixed some instruction definitions 2016-09-22 21:19:15 +02:00
flobernd 4c911f91b9 Minor bugfixes and refactorings 
* Fixed some instruction Definitions
* Implemented a primitive diffing-mode to compare different versions of the instruction-database (InstructionEditor)
 2016-09-21 20:02:09 +02:00
flobernd 317976afbf Minor bugfixes 2016-09-13 20:24:14 +02:00
flobernd 72907c6845 Added support for instructions with 5 operands 
* optimized table structure to support instructions with 5 operands (vpermil2ps, vpermil2pd)
* updated InstructionEditor
 2016-09-13 05:26:55 +02:00
flobernd 7c9a6db6af Initial version 2.0 release 2016-05-25 21:25:48 +02:00