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zydis
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Code Releases Activity
409 Commits 3 Branches 1 Tag 8.5 MiB
Commit Graph

20 Commits

Author SHA1 Message Date
flobernd 5ed561a0fc Fixed `bndldx` and `bndstx` not accepting segment-overrides 2017-10-27 03:02:36 +02:00
flobernd 38df6e0d1e Improved support for MPX instructions 2017-10-26 20:10:51 +02:00
flobernd 4de4def535 Fixed some MVEX instructions 2017-10-20 16:16:57 +02:00
flobernd 668db54b18 Added implicit operands for instructions with stack-operations 
- Implicit SP/ESP/RSP register-operand
- Implicit [SP/ESP/RSP] memory-operand
 2017-10-19 22:11:23 +02:00
flobernd 219200eebe Minor table fixes 2017-10-19 17:36:08 +02:00
flobernd 9fc44085d2 Added new ISA-extensions 
- BITALG
- GFNI
- RDPID
- VAES
- VBMI2
- VNNI
- VPCLMULQDQ
 2017-10-19 01:10:25 +02:00
flobernd 49a8f105b3 Updated instruction database 2017-09-26 21:05:50 +02:00
flobernd 10790b449f Changed immediate-operand of `aad` and `aam` from signed to unsigned 2017-09-24 22:31:17 +02:00
flobernd 6315e29aa5 Added `ZYDIS_ATTRIB_IS_FAR_BRANCH` attribute for far JMP/CALL/RET instructions 2017-09-23 18:26:48 +02:00
flobernd 9222f80b97 Fixed formatting of signed 8-bit immediate operands (again) 
- Renamed `operandSize` to `operandWidth`
- The `operandWidth` field is now set to 8-bit, if the instruction performs a byte-operation
 2017-09-21 22:16:37 +02:00
flobernd f230688af4 Fixed `ZydisISAExt` enum 2017-09-14 17:54:22 +02:00
flobernd 5914abc0be Tables fixes and more meta-info 
- Added exception-class meta-info
- Added CMake option for shared-libraries
- Fixed some instruction-definitions
- Updated VersionInfo.rc
 2017-09-06 17:05:05 +02:00
flobernd fafa93d40b Internal refactorings and new meta-info 
- Imported meta-info from Intel XED
- Added instruction-category meta-info to the `ZydisDecodedInstruction` struct
- Added isa-set meta-info to the `ZydisDecodedInstruction` struct
- Added isa-extension meta-info to the `ZydisDecodedInstruction` struct
 2017-09-05 17:35:23 +02:00
flobernd 7434bea839 Fixed some `EVEX` instruction-definitions 
- A bug in the table generator caused inverted conditions regarding zero-mask support for some `EVEX` instructions
 2017-07-25 14:30:32 +02:00
flobernd 341f3866c3 Various changes to the instruction-definitions and decoder/encoder-tables 2017-07-19 18:43:59 +02:00
flobernd 53e89b0800 Replaced `EVEX.z` filter by `acceptsZeroMask` attribute 2017-07-14 22:54:22 +02:00
flobernd 59fa404919 Added detailed information about accessed CPU-flags 2017-07-12 17:48:02 +02:00
flobernd 13a2858210 Added hidden R/E/FLAGS register operands 2017-07-12 15:44:47 +02:00
flobernd 428da82416 Added `ZYDIS_ATTRIB_IS_PRIVILEGED` 2017-07-05 13:47:54 +02:00
Joel Höner 7ba6ea0596 Moved private headers to `src` directory 2017-07-03 04:16:38 +02:00