flobernd
e481c3e401
Minor refactorings and changes to the instruction-formatter
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- The formatter now makes use of the format-macros in inttypes.h for better portability
- Added formatter-hook ZYDIS_FORMATTER_HOOK_PRINT_SEGMENT
2016-11-26 18:41:58 +01:00
Joel Höner
9a39623411
regs and flags for RCL - SWAPGS
2016-11-26 17:38:33 +01:00
flobernd
83f41f0f55
Removed unneeded files
2016-11-26 13:15:35 +01:00
flobernd
816bb570c7
Complete rewrite of the instruction-formatter
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- Added hooking functionality to support custom instruction-formatting
- Added FormatterHooks demo that demonstrates the hooking functionality
InstructionEditor:
- Fixed issues with still non-deterministic output on code-generation
2016-11-26 13:08:37 +01:00
Joel Höner
03b4d69b08
regs and flags PTWRITE - PXOR
2016-11-26 01:16:08 +01:00
Joel Höner
e2a9329781
regs and flags for PABS - PTEST
2016-11-25 20:45:17 +01:00
Joel Höner
d3d4c05246
fixed definitions for OUTS, INS
2016-11-25 18:21:09 +01:00
Joel Höner
39c1f3591e
regs and flags for MOV - OUT
2016-11-25 18:13:04 +01:00
Joel Höner
4cbc832e5c
fixed definitions for MOVS, LODS, STOS, CMPS, SCAS
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plus added a few definitions forgotten in my last commit
2016-11-25 17:13:46 +01:00
flobernd
7f1c0bd8f1
Minor refactorings and bugfixes
2016-11-24 10:57:23 +01:00
flobernd
659ead2280
Fixed second operand missing for IVLPGA
2016-11-24 10:53:00 +01:00
Joel Höner
03751240c2
regs and flags for KORTESTB - MOVAPD
2016-11-24 05:41:22 +01:00
Joel Höner
44385df1d5
regs and flags for JCC & JMP
2016-11-24 01:31:01 +01:00
Joel Höner
87b9a281cf
added flags and implicit regs for instructions DPPD-IRET
2016-11-24 00:31:49 +01:00
flobernd
32f8a798d2
Minor refactorings
2016-11-22 22:33:32 +01:00
flobernd
1159966784
Changed definition-sorting to produce deterministic output (JSON and generated tables)
2016-11-22 21:47:54 +01:00
flobernd
7f7cbd8dcd
Internal changes and optimizations of the generated tables and the InstructionEditor
2016-11-22 18:12:05 +01:00
flobernd
be56ef937d
Minor bugfixes and refactorings
2016-11-21 14:55:17 +01:00
flobernd
c4dce1adb9
Added support for test-register operands (TR0..TR7)
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- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
2016-11-14 03:39:17 +01:00
flobernd
f5610b937e
Fixed code generation and tables (again)
2016-11-14 02:53:16 +01:00
flobernd
ead586b722
Fixed code generation and tables
2016-11-14 02:22:29 +01:00
flobernd
58c73b2885
Bugfixes and Support for some more registers
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Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register
InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
2016-11-14 02:10:59 +01:00
flobernd
3f09ffca69
Minor refactorings and further preparation for advanced features
2016-11-11 22:03:26 +01:00
flobernd
98e9559d6d
Fixed some instruction definitions
2016-09-22 21:19:15 +02:00
flobernd
4c911f91b9
Minor bugfixes and refactorings
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* Fixed some instruction Definitions
* Implemented a primitive diffing-mode to compare different versions of the instruction-database (InstructionEditor)
2016-09-21 20:02:09 +02:00
flobernd
317976afbf
Minor bugfixes
2016-09-13 20:24:14 +02:00
flobernd
a636fa353e
Fixed fuzzer tool
2016-09-13 05:35:25 +02:00
flobernd
2472a86405
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2016-09-13 05:27:20 +02:00
flobernd
72907c6845
Added support for instructions with 5 operands
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* optimized table structure to support instructions with 5 operands (vpermil2ps, vpermil2pd)
* updated InstructionEditor
2016-09-13 05:26:55 +02:00
Joel Höner
5eee4a6b18
made output buffer in fuzzer input tool dynamic
2016-09-01 19:14:08 +02:00
Joel Höner
589c4ae691
added stuff forgotten in previous commit
2016-08-28 23:12:40 +02:00
Joel Höner
a947d86539
added tool for fuzzing the disassembler
2016-08-28 23:08:07 +02:00
flobernd
0cfed163a0
Commited internally used InstructionEditor
2016-08-23 16:11:42 +02:00
flobernd
54f2bc43ac
Preparations for optional feature support
2016-08-23 15:58:40 +02:00
flobernd
a6e76d81b4
Preparations for optional feature support
2016-08-23 15:57:38 +02:00
flobernd
52dd9fac89
Fixed CMake file
2016-06-20 01:33:29 +02:00
flobernd
7c9a6db6af
Initial version 2.0 release
2016-05-25 21:25:48 +02:00
athre0z
f377f7b559
use an example with a little more interesting output
2016-04-15 22:11:49 +02:00
Ingve Vormestrand
92715986fa
Added sample output to README
2016-04-06 00:15:12 +02:00
flobernd
aa684c1bcc
Fixed invalid decoding of INSERTPS instruction
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closes #4
2016-03-23 18:06:42 +01:00
Joel Höner
f8ed7e1bac
fixed travis
2016-02-05 08:42:21 +01:00
Joel Höner
44c3b6b2b0
fixed invalid array access
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- an invalid array access could crash on decoding some 3D-Now instructions
2015-12-08 19:19:34 +01:00
athre0z
df84e70229
updated version info
2015-05-22 17:50:52 +02:00
athre0z
5bab2410fc
Merge branch 'develop'
2015-05-22 17:45:06 +02:00
athre0z
2070b7a427
improved documentation and README.md
2015-05-22 17:23:32 +02:00
flobernd
1e51b9a69d
Fixed readme
2015-05-21 22:59:24 +02:00
flobernd
e534fdf6e2
Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop
2015-05-21 21:42:33 +02:00
flobernd
02d0d84c68
Minor bugfixes
2015-05-21 21:42:06 +02:00
athre0z
907fb1e1f2
updated Doxyfile
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[skip ci]
2015-05-21 21:22:11 +02:00
athre0z
9572b08daf
fixed formatted printing
2015-05-21 17:35:26 +02:00