x64dbg
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zydis
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235 Commits 3 Branches 1 Tag 8.5 MiB
Commit Graph

26 Commits

Author SHA1 Message Date
flobernd b3d508850f Added information for VEX/EVEX/MVEX instructions with static broadcast-factor 2017-06-23 20:47:34 +02:00
flobernd c8c3d29ba4 Added support for MVEX instructions with static broadcast factor 2017-06-23 03:35:12 +02:00
flobernd 2297c763cf Added compressed disp8 calculation for MVEX instructions with element-granularity 2017-06-23 01:40:19 +02:00
flobernd d8f3843f57 Added compressed disp8 calculation for MVEX instructions without swizzle/broadcast/convert functionality 2017-06-23 01:15:42 +02:00
flobernd 6c370d29c9 Added support for some MVEX special-cases 2017-06-22 22:10:18 +02:00
flobernd 4d3a71369b Removed EVEX tuple-type and element-size from the public info-struct 2017-06-22 19:54:35 +02:00
flobernd 76f0bcf00d Improved semantic decoding of MVEX instructions 2017-06-22 19:14:27 +02:00
flobernd 15f89dc4ea Fixed a bitfield-size error 2017-06-22 01:40:20 +02:00
flobernd 5bd81b7f1c Fixed sign-extension of displacement values 2017-06-22 01:38:41 +02:00
flobernd d475231a63 Fixed decoding of implicit "1" immediate (ROL, ROR, RCL, ...) 2017-06-20 22:44:37 +02:00
flobernd 52e1b59702 Improved EVEX and MVEX encoding 
- Added some MASK related error-conditions
- Added functionality and mask-policy attributes to the MVEX instruction-definition struct
- Added MVEX specific error-condition
 2017-06-20 21:23:06 +02:00
flobernd 4bceac86c9 Various bugfixes 
- Fixed operand-size and element-count of AGEN operands
- Fixed decoding of 8-bit modrm.rm register-operands
- Fixed vector-length for EVEX instructions with rounding-semantics
 2017-06-19 20:19:21 +02:00
flobernd ad35e81eee Added semantic element-information for operands 2017-06-16 23:19:57 +02:00
flobernd 44792f2338 Added semantic decoding of implicit memory operands 2017-06-16 16:27:37 +02:00
flobernd 1db4db9ec2 Added semantic decoding of implicit register operands 2017-06-16 03:25:39 +02:00
flobernd 6caa68b674 Reimplemented decoding of 3DNOW instructions and improved EVEX decoding 2017-06-13 22:04:29 +02:00
flobernd 702f6b8d53 Reimplemented a basic version of semantic operand-decoding 2017-06-13 20:17:20 +02:00
flobernd 8740b1e50f Major changes to the instruction decoder 
- Decoupled semantic operand decoding (optional) from physical instruction decoding
- Several optimizations of the internal structures
- Further preparations for MVEX-support
 2017-06-12 19:16:01 +02:00
Joel Höner 689708fbd3 Refactored docstrings to use uppercase abbreviations 2017-01-12 19:37:57 +01:00
flobernd 5b63557f3c Fixed decoding of instructions with EVEX high-16 register specifiers (R', X, V') 2016-12-05 21:06:29 +01:00
flobernd d4dd176438 Refactorings and bugfixes 
- Added support for the BOUND prefix
- Added support for more detailed operand-actions (read, write, readwrite, cond. read, cond. write, read + cond. write, write + cond. read)
- Added operand-visibility info (explicit, implicit, hidden)
- Fixed some bugs in the prefix-decoding routines
- Removed stdbool.h dependency and introduced custom boolean-type for better portability
 2016-12-05 02:24:01 +01:00
flobernd 7f1c0bd8f1 Minor refactorings and bugfixes 2016-11-24 10:57:23 +01:00
flobernd 7f7cbd8dcd Internal changes and optimizations of the generated tables and the InstructionEditor 2016-11-22 18:12:05 +01:00
flobernd c4dce1adb9 Added support for test-register operands (TR0..TR7) 
- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
 2016-11-14 03:39:17 +01:00
flobernd 72907c6845 Added support for instructions with 5 operands 
* optimized table structure to support instructions with 5 operands (vpermil2ps, vpermil2pd)
* updated InstructionEditor
 2016-09-13 05:26:55 +02:00
flobernd 7c9a6db6af Initial version 2.0 release 2016-05-25 21:25:48 +02:00