Commit Graph

17 Commits

Author SHA1 Message Date
flobernd 3b56c867fc Updated mask-policy definitions for EVEX instructions 2017-01-11 22:11:30 +01:00
flobernd 5b63557f3c Fixed decoding of instructions with EVEX high-16 register specifiers (R', X, V') 2016-12-05 21:06:29 +01:00
flobernd d4dd176438 Refactorings and bugfixes
- Added support for the BOUND prefix
- Added support for more detailed operand-actions (read, write, readwrite, cond. read, cond. write, read + cond. write, write + cond. read)
- Added operand-visibility info (explicit, implicit, hidden)
- Fixed some bugs in the prefix-decoding routines
- Removed stdbool.h dependency and introduced custom boolean-type for better portability
2016-12-05 02:24:01 +01:00
flobernd bb913f1272 Fixed some instruction-definitions and re-generated tables 2016-11-29 23:48:10 +01:00
flobernd 816bb570c7 Complete rewrite of the instruction-formatter
- Added hooking functionality to support custom instruction-formatting
- Added FormatterHooks demo that demonstrates the hooking functionality

InstructionEditor:
- Fixed issues with still non-deterministic output on code-generation
2016-11-26 13:08:37 +01:00
flobernd 7f1c0bd8f1 Minor refactorings and bugfixes 2016-11-24 10:57:23 +01:00
flobernd 1159966784 Changed definition-sorting to produce deterministic output (JSON and generated tables) 2016-11-22 21:47:54 +01:00
flobernd 7f7cbd8dcd Internal changes and optimizations of the generated tables and the InstructionEditor 2016-11-22 18:12:05 +01:00
flobernd c4dce1adb9 Added support for test-register operands (TR0..TR7)
- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
2016-11-14 03:39:17 +01:00
flobernd f5610b937e Fixed code generation and tables (again) 2016-11-14 02:53:16 +01:00
flobernd ead586b722 Fixed code generation and tables 2016-11-14 02:22:29 +01:00
flobernd 58c73b2885 Bugfixes and Support for some more registers
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
2016-11-14 02:10:59 +01:00
flobernd 98e9559d6d Fixed some instruction definitions 2016-09-22 21:19:15 +02:00
flobernd 4c911f91b9 Minor bugfixes and refactorings
* Fixed some instruction Definitions
* Implemented a primitive diffing-mode to compare different versions of the instruction-database (InstructionEditor)
2016-09-21 20:02:09 +02:00
flobernd 317976afbf Minor bugfixes 2016-09-13 20:24:14 +02:00
flobernd 72907c6845 Added support for instructions with 5 operands
* optimized table structure to support instructions with 5 operands (vpermil2ps, vpermil2pd)
* updated InstructionEditor
2016-09-13 05:26:55 +02:00
flobernd 7c9a6db6af Initial version 2.0 release 2016-05-25 21:25:48 +02:00