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zydis
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176 Commits 3 Branches 1 Tag 8.5 MiB
Commit Graph

48 Commits

Author SHA1 Message Date
flobernd 3b56c867fc Updated mask-policy definitions for EVEX instructions 2017-01-11 22:11:30 +01:00
Joel Höner cbc9460547 Added tool for testing Zydis against CPU behaviour (Intel PIN) 2017-01-06 02:04:21 +01:00
flobernd 5b63557f3c Fixed decoding of instructions with EVEX high-16 register specifiers (R', X, V') 2016-12-05 21:06:29 +01:00
flobernd d4dd176438 Refactorings and bugfixes 
- Added support for the BOUND prefix
- Added support for more detailed operand-actions (read, write, readwrite, cond. read, cond. write, read + cond. write, write + cond. read)
- Added operand-visibility info (explicit, implicit, hidden)
- Fixed some bugs in the prefix-decoding routines
- Removed stdbool.h dependency and introduced custom boolean-type for better portability
 2016-12-05 02:24:01 +01:00
flobernd bb913f1272 Fixed some instruction-definitions and re-generated tables 2016-11-29 23:48:10 +01:00
flobernd 879f456b03 Fixed some instruction-definitions 2016-11-29 18:30:39 +01:00
flobernd 2e58e13d81 Fixed some instruction-definitions 2016-11-29 13:50:15 +01:00
flobernd 5480ad0aaf Fixed some instruction-definitions 2016-11-29 13:21:09 +01:00
flobernd 425a0d6cd7 Fixed some operand-definitions 2016-11-29 12:38:01 +01:00
flobernd e926c26d6e Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2016-11-29 11:47:32 +01:00
Joel Höner 75921f9ca6 Altered instruction DB format 
- support for multiple flag operations
- various definition fixes based on newly enabled editor heuristics
 2016-11-28 23:25:26 +01:00
flobernd bfcbe3e8c1 Minor bugfixes and refactorings 2016-11-28 15:03:39 +01:00
flobernd 477a908bb0 Added more formatter-hooks 
- ZYDIS_FORMATTER_HOOK_PRINT_DISPLACEMENT
- ZYDIS_FORMATTER_HOOK_PRINT_IMMEDIATE
 2016-11-28 11:14:47 +01:00
flobernd 805a407395 Merge branch 'develop' of github.com:zyantific/zyan-disassembler-engine into develop 2016-11-28 10:48:10 +01:00
Joel Höner 05d36bd39b fixed many inaccurate flag definitions 2016-11-28 02:44:17 +01:00
flobernd 25f5dfeff1 Added missing x86-flags 2016-11-27 23:54:55 +01:00
flobernd 9a0b1da975 Added missing registers and CPUID feature-flags 2016-11-27 23:24:43 +01:00
Joel Höner 9ce1ba1b3b regs and flags for Intel VT-x instructions 2016-11-27 22:35:38 +01:00
Joel Höner e4f89a05ee regs and flags for VSCALEFPD - XTEST 2016-11-27 19:40:22 +01:00
Joel Höner 08d7a198f3 regs and flags for VFNMADD132PD - VRSQRT28SS 2016-11-27 00:14:27 +01:00
Joel Höner 6240bb8f7d regs and flags for SYSCALL - VFMSUB231SS 2016-11-26 20:43:33 +01:00
Joel Höner 9a39623411 regs and flags for RCL - SWAPGS 2016-11-26 17:38:33 +01:00
flobernd 816bb570c7 Complete rewrite of the instruction-formatter 
- Added hooking functionality to support custom instruction-formatting
- Added FormatterHooks demo that demonstrates the hooking functionality

InstructionEditor:
- Fixed issues with still non-deterministic output on code-generation
 2016-11-26 13:08:37 +01:00
Joel Höner 03b4d69b08 regs and flags PTWRITE - PXOR 2016-11-26 01:16:08 +01:00
Joel Höner e2a9329781 regs and flags for PABS - PTEST 2016-11-25 20:45:17 +01:00
Joel Höner d3d4c05246 fixed definitions for OUTS, INS 2016-11-25 18:21:09 +01:00
Joel Höner 39c1f3591e regs and flags for MOV - OUT 2016-11-25 18:13:04 +01:00
Joel Höner 4cbc832e5c fixed definitions for MOVS, LODS, STOS, CMPS, SCAS 
plus added a few definitions forgotten in my last commit
 2016-11-25 17:13:46 +01:00
flobernd 7f1c0bd8f1 Minor refactorings and bugfixes 2016-11-24 10:57:23 +01:00
flobernd 659ead2280 Fixed second operand missing for IVLPGA 2016-11-24 10:53:00 +01:00
Joel Höner 03751240c2 regs and flags for KORTESTB - MOVAPD 2016-11-24 05:41:22 +01:00
Joel Höner 44385df1d5 regs and flags for JCC & JMP 2016-11-24 01:31:01 +01:00
Joel Höner 87b9a281cf added flags and implicit regs for instructions DPPD-IRET 2016-11-24 00:31:49 +01:00
flobernd 32f8a798d2 Minor refactorings 2016-11-22 22:33:32 +01:00
flobernd 1159966784 Changed definition-sorting to produce deterministic output (JSON and generated tables) 2016-11-22 21:47:54 +01:00
flobernd 7f7cbd8dcd Internal changes and optimizations of the generated tables and the InstructionEditor 2016-11-22 18:12:05 +01:00
flobernd c4dce1adb9 Added support for test-register operands (TR0..TR7) 
- New instructions: "mov TR, GPR32" and "mov GPR32, TR"
 2016-11-14 03:39:17 +01:00
flobernd f5610b937e Fixed code generation and tables (again) 2016-11-14 02:53:16 +01:00
flobernd ead586b722 Fixed code generation and tables 2016-11-14 02:22:29 +01:00
flobernd 58c73b2885 Bugfixes and Support for some more registers 
Zydis:
- Fixed operand-size of some instructions in 64-bit mode
- Fixed operand decoding of the "movq MM, GPR" instruction
- Added table-registers (GDRT, LDTR, IDTR, TR)
- Added test-registers (TR0..TR7)
- Added BNDCFG and BNDSTATUS registers
- Added MXCR register

InstructionEditor:
- The code-generator now eliminates duplicate instruction-definitions to optimize the size of the generated tables
- Fixed conflict indication for some operand type/encoding combinations
- Added conflict indication for X86Flags
 2016-11-14 02:10:59 +01:00
flobernd 3f09ffca69 Minor refactorings and further preparation for advanced features 2016-11-11 22:03:26 +01:00
flobernd 98e9559d6d Fixed some instruction definitions 2016-09-22 21:19:15 +02:00
flobernd 4c911f91b9 Minor bugfixes and refactorings 
* Fixed some instruction Definitions
* Implemented a primitive diffing-mode to compare different versions of the instruction-database (InstructionEditor)
 2016-09-21 20:02:09 +02:00
flobernd 317976afbf Minor bugfixes 2016-09-13 20:24:14 +02:00
flobernd a636fa353e Fixed fuzzer tool 2016-09-13 05:35:25 +02:00
flobernd 72907c6845 Added support for instructions with 5 operands 
* optimized table structure to support instructions with 5 operands (vpermil2ps, vpermil2pd)
* updated InstructionEditor
 2016-09-13 05:26:55 +02:00
flobernd 0cfed163a0 Commited internally used InstructionEditor 2016-08-23 16:11:42 +02:00
flobernd 7c9a6db6af Initial version 2.0 release 2016-05-25 21:25:48 +02:00