Added support for test-register operands (TR0..TR7)

- New instructions: "mov TR, GPR32" and "mov GPR32, TR"

assets/InstructionEditor/Zydis.CodeGenerator.pas

@@ -845,6 +845,7 @@ begin
     optVR128      : OperandType := 'VR128';
     optVR256      : OperandType := 'VR256';
     optVR512      : OperandType := 'VR512';
+    optTR         : OperandType := 'TR';
     optCR         : OperandType := 'CR';
     optDR         : OperandType := 'DR';
     optMSKR       : OperandType := 'MSKR';

assets/InstructionEditor/Zydis.InstructionEditor.pas

@@ -368,6 +368,7 @@ type
     optVR128,
     optVR256,
     optVR512,
+    optTR,
     optCR,
     optDR,
     optSREG,
@@ -1081,6 +1082,7 @@ const
     'vr128',
     'vr256',
     'vr512',
+    'tr',
     'cr',
     'dr',
     'sreg',
@@ -1975,6 +1977,7 @@ begin
       Result := not (FEncoding in [opeModrmReg, opeModrmRm, opeVexVVVV, opeImm8Hi, opeModrmRmCD1,
         opeModrmRmCD2, opeModrmRmCD4, opeModrmRmCD8, opeModrmRmCD16, opeModrmRmCD32,
         opeModrmRmCD64]);
+    optTR,
     optCR,
     optDR,
     optSREG:
@@ -2093,6 +2096,7 @@ begin
       optVR512     : Result := 'ZMM512';
       optMSKR      : Result := 'MASK';
       optBNDR      : Result := 'BND';
+      optTR        : Result := 'TR';
       optCR        : Result := 'CR';
       optDR        : Result := 'DR';
       optMem       : Result := 'mem';
@@ -2241,8 +2245,10 @@ begin
       optVR512: ;
       optFPR:
         FEncoding := opeModrmRm;
-      optCR: ;
-      optDR: ;
+      optTR,
+      optCR,
+      optDR:
+        FEncoding := opeModrmReg;
       optSREG: ;
       optMSKR: ;
       optBNDR: ;

include/Zydis/Internal/InstructionTable.h

@@ -173,6 +173,7 @@ enum ZydisSemanticOperandTypes
     ZYDIS_SEM_OPERAND_TYPE_VR128,
     ZYDIS_SEM_OPERAND_TYPE_VR256,
     ZYDIS_SEM_OPERAND_TYPE_VR512,
+    ZYDIS_SEM_OPERAND_TYPE_TR,
     ZYDIS_SEM_OPERAND_TYPE_CR,
     ZYDIS_SEM_OPERAND_TYPE_DR,
     ZYDIS_SEM_OPERAND_TYPE_SREG,

src/Decoder.c

@@ -999,6 +999,10 @@ static ZydisDecoderStatus ZydisDecodeOperand(ZydisInstructionDecoder* decoder,
         operand->size = 64;
         registerClass = ZYDIS_REGISTERCLASS_GENERAL_PURPOSE64;
         break;
+    case ZYDIS_SEM_OPERAND_TYPE_TR:
+        operand->size = 32; // TODO: ?
+        registerClass = ZYDIS_REGISTERCLASS_TEST;
+        break;
     case ZYDIS_SEM_OPERAND_TYPE_CR:
         operand->size = (decoder->disassemblerMode == ZYDIS_DISASSEMBLER_MODE_64BIT) ? 64 : 32;
         registerClass = ZYDIS_REGISTERCLASS_CONTROL;