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zydis
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Minor bugfixes 

- Fixed some VEX/EVEX/MVEX-prefix error conditions
- MASK register size is now 64-bit for EVEX- and 16-bit for MVEX-instructions
This commit is contained in:
flobernd 2017-06-20 17:48:55 +02:00
parent 17358016d9
commit 95b685a29d
4 changed files with 10232 additions and 10199 deletions
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10626
include/Zydis/Internal/InstructionDefinitions.inc
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File diff suppressed because it is too large Load Diff

9780
include/Zydis/Internal/OperandDefinitions.inc
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File diff suppressed because it is too large Load Diff

23
src/Decoder.c
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@ -326,8 +326,7 @@ static ZydisStatus ZydisDecodeVEX(ZydisDecoderContext* context, ZydisInstruction
ZYDIS_UNREACHABLE; ZYDIS_UNREACHABLE;
} }
// TODO: map = 0 is allowed for some newer VEX instructions if (info->details.vex.m_mmmm > 0x03)
if (/*(info->details.vex.m_mmmm == 0x00) || */(info->details.vex.m_mmmm > 0x03))
{ {
// Invalid according to the intel documentation // Invalid according to the intel documentation
return ZYDIS_STATUS_INVALID_MAP; return ZYDIS_STATUS_INVALID_MAP;
@ -380,12 +379,11 @@ static ZydisStatus ZydisDecodeEVEX(ZydisDecoderContext* context, ZydisInstructio
info->details.evex.mm = (data[1] >> 0) & 0x03; info->details.evex.mm = (data[1] >> 0) & 0x03;
// TODO: Check if map = 0 is allowed for new EVEX instructions // TODO: Check if map = 0 is allowed for new EVEX instructions
if (info->details.evex.mm == 0x00)
//if (info->details.evex.mm == 0x00) {
//{ // Invalid according to the intel documentation
// // Invalid according to the intel documentation return ZYDIS_STATUS_INVALID_MAP;
// return ZYDIS_STATUS_INVALID_MAP; }
//}
info->details.evex.W = (data[2] >> 7) & 0x01; info->details.evex.W = (data[2] >> 7) & 0x01;
info->details.evex.vvvv = (data[2] >> 3) & 0x0F; info->details.evex.vvvv = (data[2] >> 3) & 0x0F;
@ -411,6 +409,10 @@ static ZydisStatus ZydisDecodeEVEX(ZydisDecoderContext* context, ZydisInstructio
context->cache.v_vvvv = context->cache.v_vvvv =
((0x01 & ~info->details.evex.V2) << 4) | (0x0F & ~info->details.evex.vvvv); ((0x01 & ~info->details.evex.V2) << 4) | (0x0F & ~info->details.evex.vvvv);
if (!info->details.evex.V2 && (context->decoder->machineMode != 64))
{
return ZYDIS_STATUS_MALFORMED_EVEX;
}
if (!info->details.evex.b && (context->cache.LL == 3)) if (!info->details.evex.b && (context->cache.LL == 3))
{ {
// LL = 3 is only valid for instructions with embedded rounding control // LL = 3 is only valid for instructions with embedded rounding control
@ -447,8 +449,7 @@ static ZydisStatus ZydisDecodeMVEX(ZydisDecoderContext* context, ZydisInstructio
info->details.mvex.R2 = (data[1] >> 4) & 0x01; info->details.mvex.R2 = (data[1] >> 4) & 0x01;
info->details.mvex.mmmm = (data[1] >> 0) & 0x0F; info->details.mvex.mmmm = (data[1] >> 0) & 0x0F;
// TODO: Check if map = 0 is allowed for new MVEX instructions if (info->details.mvex.mmmm > 0x03)
if (/*(info->details.mvex.mmmm == 0x00) || */(info->details.mvex.mmmm > 0x03))
{ {
// Invalid according to the intel documentation // Invalid according to the intel documentation
return ZYDIS_STATUS_INVALID_MAP; return ZYDIS_STATUS_INVALID_MAP;
@ -3177,7 +3178,7 @@ ZydisStatus ZydisDecoderInitInstructionDecoderEx(ZydisInstructionDecoder* decode
addressWidth = ZYDIS_ADDRESS_WIDTH_64; addressWidth = ZYDIS_ADDRESS_WIDTH_64;
} else } else
{ {
if ((addressWidth != 16) && (addressWidth != 32) && (addressWidth != 64)) if ((addressWidth != 16) && (addressWidth != 32))
{ {
return ZYDIS_STATUS_INVALID_PARAMETER; return ZYDIS_STATUS_INVALID_PARAMETER;
} }

2
src/Register.c
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@ -148,7 +148,7 @@ static const struct ZydisRegisterMapItem registerMap[] =
{ ZYDIS_REGCLASS_TEST , ZYDIS_REGISTER_TR0 , ZYDIS_REGISTER_TR7 , 32 , 32 }, { ZYDIS_REGCLASS_TEST , ZYDIS_REGISTER_TR0 , ZYDIS_REGISTER_TR7 , 32 , 32 },
{ ZYDIS_REGCLASS_CONTROL , ZYDIS_REGISTER_CR0 , ZYDIS_REGISTER_CR15 , 32 , 64 }, { ZYDIS_REGCLASS_CONTROL , ZYDIS_REGISTER_CR0 , ZYDIS_REGISTER_CR15 , 32 , 64 },
{ ZYDIS_REGCLASS_DEBUG , ZYDIS_REGISTER_DR0 , ZYDIS_REGISTER_DR15 , 32 , 64 }, { ZYDIS_REGCLASS_DEBUG , ZYDIS_REGISTER_DR0 , ZYDIS_REGISTER_DR15 , 32 , 64 },
{ ZYDIS_REGCLASS_MASK , ZYDIS_REGISTER_K0 , ZYDIS_REGISTER_K7 , 64 , 64 }, { ZYDIS_REGCLASS_MASK , ZYDIS_REGISTER_K0 , ZYDIS_REGISTER_K7 , 0 , 0 },
{ ZYDIS_REGCLASS_BOUND , ZYDIS_REGISTER_BND0 , ZYDIS_REGISTER_BND3 , 128 , 128 } { ZYDIS_REGCLASS_BOUND , ZYDIS_REGISTER_BND0 , ZYDIS_REGISTER_BND3 , 128 , 128 }
}; };