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zydis
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Bugfixes and table changes 

- Fixed `SSE4A` ISA-set and ISA-ext
- Added missing `VEX`-encoded `GFNI` instructions
- Added check for invalid `GATHER`/`SCATTER` registers
This commit is contained in:
flobernd 2018-01-11 02:17:17 +01:00
parent 407a527ae7
commit 7fb7eea11f
No known key found for this signature in database
GPG Key ID: 9C3AE0ED4A969F10
8 changed files with 5862 additions and 5778 deletions
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2
include/Zydis/Generated/EnumISAExt.h
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@ -70,6 +70,7 @@ enum ZydisISAExts
ZYDIS_ISA_EXT_AVX512_VPOPCNTDQ_256,
ZYDIS_ISA_EXT_AVX512_VPOPCNTDQ_512,
ZYDIS_ISA_EXT_AVXAES,
ZYDIS_ISA_EXT_AVX_GFNI,
ZYDIS_ISA_EXT_BMI1,
ZYDIS_ISA_EXT_BMI2,
ZYDIS_ISA_EXT_CET,
@ -136,6 +137,7 @@ enum ZydisISAExts
ZYDIS_ISA_EXT_SSE3X87,
ZYDIS_ISA_EXT_SSE4,
ZYDIS_ISA_EXT_SSE42,
ZYDIS_ISA_EXT_SSE4A,
ZYDIS_ISA_EXT_SSEMXCSR,
ZYDIS_ISA_EXT_SSE_PREFETCH,
ZYDIS_ISA_EXT_SSSE3,

8
include/Zydis/Internal/SharedData.h
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@ -593,7 +593,7 @@ enum ZydisMaskPolicies
ZYDIS_INSTRUCTION_DEFINITION_BASE; \
ZydisRegisterConstraint constrNDSNDD ZYDIS_BITFIELD(ZYDIS_REG_CONSTRAINTS_MIN_BITS)
#define ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_EX \
#define ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_INTEL \
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR; \
ZydisBool hasVSIB ZYDIS_BITFIELD( 1)
@ -646,7 +646,7 @@ typedef struct ZydisInstructionDefinitionXOP_
*/
typedef struct ZydisInstructionDefinitionVEX_
{
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR;
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_INTEL;
ZydisVEXStaticBroadcast broadcast ZYDIS_BITFIELD( 3);
} ZydisInstructionDefinitionVEX;
@ -656,7 +656,7 @@ typedef struct ZydisInstructionDefinitionVEX_
*/
typedef struct ZydisInstructionDefinitionEVEX_
{
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_EX;
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_INTEL;
ZydisInternalVectorLength vectorLength ZYDIS_BITFIELD( 2);
ZydisEVEXTupleType tupleType ZYDIS_BITFIELD( 4);
ZydisInternalElementSize elementSize ZYDIS_BITFIELD( 3);
@ -674,7 +674,7 @@ typedef struct ZydisInstructionDefinitionEVEX_
*/
typedef struct ZydisInstructionDefinitionMVEX_
{
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_EX;
ZYDIS_INSTRUCTION_DEFINITION_BASE_VECTOR_INTEL;
ZydisMVEXFunctionality functionality ZYDIS_BITFIELD( 5);
ZydisMaskPolicy maskPolicy ZYDIS_BITFIELD( 2);
ZydisBool hasElementGranularity ZYDIS_BITFIELD( 1);

37
src/Decoder.c
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@ -4053,6 +4053,7 @@ static ZydisStatus ZydisCheckErrorConditions(ZydisDecoderContext* context,
const ZydisInstructionDefinitionVEX* def =
(const ZydisInstructionDefinitionVEX*)definition;
constrNDSNDD = def->constrNDSNDD;
hasVSIB = def->hasVSIB;
break;
}
case ZYDIS_INSTRUCTION_ENCODING_EVEX:
@ -4289,6 +4290,38 @@ static ZydisStatus ZydisCheckErrorConditions(ZydisDecoderContext* context,
ZYDIS_UNREACHABLE;
}
// Check gather/scatter registers
if (hasVSIB)
{
ZYDIS_ASSERT(instruction->raw.modrm.mod != 3);
ZYDIS_ASSERT(instruction->raw.modrm.rm == 4);
const ZydisU8 dest = instruction->raw.modrm.reg | (context->cache.R << 3) |
(context->cache.R2 << 4);
const ZydisU8 index = instruction->raw.sib.index | (context->cache.X << 3) |
(context->cache.V2 << 4);
ZydisU8 mask = 0xFF;
switch (instruction->encoding)
{
case ZYDIS_INSTRUCTION_ENCODING_VEX:
ZYDIS_ASSERT(!constrREG && !constrRM && !constrNDSNDD);
mask = context->cache.v_vvvv;
break;
case ZYDIS_INSTRUCTION_ENCODING_EVEX:
case ZYDIS_INSTRUCTION_ENCODING_MVEX:
ZYDIS_ASSERT(!constrREG && !constrRM && constrNDSNDD == ZYDIS_REG_CONSTRAINTS_UNUSED);
break;
default:
ZYDIS_UNREACHABLE;
}
// If any pair of the index, mask, or destination registers are the same, the instruction
// results a UD fault.
if (dest == index || dest == mask || index == mask)
{
return ZYDIS_STATUS_BAD_REGISTER;
}
}
#if !defined(ZYDIS_DISABLE_EVEX) || !defined(ZYDIS_DISABLE_MVEX)
// Check for invalid MASK registers
switch (maskPolicy)
@ -4442,13 +4475,13 @@ static ZydisStatus ZydisDecodeInstruction(ZydisDecoderContext* context,
{
const ZydisInstructionDefinition* definition;
ZydisGetInstructionDefinition(instruction->encoding, node->value, &definition);
ZYDIS_CHECK(ZydisCheckErrorConditions(context, instruction, definition));
ZydisSetEffectiveOperandSize(context, instruction, definition);
ZydisSetEffectiveAddressWidth(context, instruction, definition);
const ZydisInstructionEncodingInfo* info;
ZydisGetInstructionEncodingInfo(node, &info);
ZYDIS_CHECK(ZydisDecodeOptionalInstructionParts(context, instruction, info));
ZYDIS_CHECK(ZydisCheckErrorConditions(context, instruction, definition));
if (instruction->encoding == ZYDIS_INSTRUCTION_ENCODING_3DNOW)
{
@ -4597,8 +4630,6 @@ ZydisStatus ZydisDecoderDecodeBuffer(const ZydisDecoder* decoder, const void* bu
ZYDIS_CHECK(ZydisCollectOptionalPrefixes(&context, instruction));
ZYDIS_CHECK(ZydisDecodeInstruction(&context, instruction));
// TODO: The index, dest and mask regs for AVX2 gathers must be different.
// TODO: More EVEX UD conditions (page 81)
return ZYDIS_STATUS_SUCCESS;

1199
src/Generated/DecoderTables.inc
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File diff suppressed because one or more lines are too long

2
src/Generated/EnumISAExt.inc
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@ -62,6 +62,7 @@ static const char* zydisISAExtStrings[] =
"AVX512_VPOPCNTDQ_256",
"AVX512_VPOPCNTDQ_512",
"AVXAES",
"AVX_GFNI",
"BMI1",
"BMI2",
"CET",
@ -128,6 +129,7 @@ static const char* zydisISAExtStrings[] =
"SSE3X87",
"SSE4",
"SSE42",
"SSE4A",
"SSEMXCSR",
"SSE_PREFETCH",
"SSSE3",

2
src/Generated/EnumISASet.inc
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@ -52,7 +52,7 @@ static const char* zydisISASetStrings[] =
"SSE2",
"SSE3",
"SSE4",
"SSE4a",
"SSE4A",
"SSSE3",
"SVM",
"TBM",

10374
src/Generated/InstructionDefinitions.inc
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File diff suppressed because it is too large Load Diff

16
src/Generated/OperandDefinitions.inc
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@ -1682,6 +1682,22 @@ const ZydisOperandDefinition operandDefinitions[] =
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_FLOAT32, { .encoding = ZYDIS_OPERAND_ENCODING_NDSNDD } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_FLOAT32, { .encoding = ZYDIS_OPERAND_ENCODING_IS4 } },
{ ZYDIS_SEMANTIC_OPTYPE_MEM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 4, 4, 4 }, ZYDIS_IELEMENT_TYPE_FLOAT32, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_RM } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_WRITE, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_REG } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_NDSNDD } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_UINT64, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_RM } },
{ ZYDIS_SEMANTIC_OPTYPE_IMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 1, 1, 1 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_UIMM8 } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_WRITE, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_REG } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_NDSNDD } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_UINT64, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_RM } },
{ ZYDIS_SEMANTIC_OPTYPE_IMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 1, 1, 1 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_UIMM8 } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_WRITE, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_REG } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_NDSNDD } },
{ ZYDIS_SEMANTIC_OPTYPE_MEM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_UINT64, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_RM } },
{ ZYDIS_SEMANTIC_OPTYPE_IMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 1, 1, 1 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_UIMM8 } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_WRITE, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_REG } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_NDSNDD } },
{ ZYDIS_SEMANTIC_OPTYPE_MEM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_UINT64, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_RM } },
{ ZYDIS_SEMANTIC_OPTYPE_IMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 1, 1, 1 }, ZYDIS_IELEMENT_TYPE_UINT8, { .encoding = ZYDIS_OPERAND_ENCODING_UIMM8 } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_WRITE, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_FLOAT64, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_REG } },
{ ZYDIS_SEMANTIC_OPTYPE_YMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 32, 32, 32 }, ZYDIS_IELEMENT_TYPE_FLOAT64, { .encoding = ZYDIS_OPERAND_ENCODING_NDSNDD } },
{ ZYDIS_SEMANTIC_OPTYPE_XMM, ZYDIS_OPERAND_VISIBILITY_EXPLICIT, ZYDIS_OPERAND_ACTION_READ, { 16, 16, 16 }, ZYDIS_IELEMENT_TYPE_FLOAT64, { .encoding = ZYDIS_OPERAND_ENCODING_MODRM_RM } },