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/**************************************************************************************************
Verteron Disassembler Engine
Version 1.0
Remarks : Freeware , Copyright must be included
Original Author : Florian Bernd
Modifications :
Last change : 14. October 2014
* Permission is hereby granted , free of charge , to any person obtaining a copy
* of this software and associated documentation files ( the " Software " ) , to deal
* in the Software without restriction , including without limitation the rights
* to use , copy , modify , merge , publish , distribute , sublicense , and / or sell
* copies of the Software , and to permit persons to whom the Software is
* furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING FROM ,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE .
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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# include "VXOpcodeTable.hpp"
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namespace Verteron
{
namespace Internal
{
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# define VX_INVALID 0
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# define NODE(type, n) (static_cast<VXOpcodeTreeNode>(type) << 12 | (n))
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const VXOpcodeTreeNode optreeTable [ ] [ 256 ] =
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{
{
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/* 00 */ 0x0015 ,
/* 01 */ 0x0014 ,
/* 02 */ 0x0016 ,
/* 03 */ 0x0018 ,
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/* 04 */ 0x0017 ,
/* 05 */ 0x0010 ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0000 ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0001 ) ,
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/* 08 */ 0x0394 ,
/* 09 */ 0x0393 ,
/* 0A */ 0x0396 ,
/* 0B */ 0x0395 ,
/* 0C */ 0x0390 ,
/* 0D */ 0x038F ,
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/* 0E */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0002 ) ,
/* 0F */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0001 ) ,
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/* 10 */ 0x000B ,
/* 11 */ 0x000A ,
/* 12 */ 0x000C ,
/* 13 */ 0x000E ,
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/* 14 */ 0x000D ,
/* 15 */ 0x0006 ,
/* 16 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0007 ) ,
/* 17 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0008 ) ,
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/* 18 */ 0x04FE ,
/* 19 */ 0x04F7 ,
/* 1A */ 0x04F8 ,
/* 1B */ 0x04FB ,
/* 1C */ 0x04FA ,
/* 1D */ 0x04F9 ,
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/* 1E */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0009 ) ,
/* 1F */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x000A ) ,
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/* 20 */ 0x0026 ,
/* 21 */ 0x0027 ,
/* 22 */ 0x0025 ,
/* 23 */ 0x002C ,
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/* 24 */ 0x002D ,
/* 25 */ 0x002E ,
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/* 26 */ VX_INVALID ,
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/* 27 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x000B ) ,
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/* 28 */ 0x0542 ,
/* 29 */ 0x0549 ,
/* 2A */ 0x0548 ,
/* 2B */ 0x054B ,
/* 2C */ 0x054A ,
/* 2D */ 0x0547 ,
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/* 2E */ VX_INVALID ,
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/* 2F */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x000C ) ,
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/* 30 */ 0x06B8 ,
/* 31 */ 0x06B9 ,
/* 32 */ 0x06B6 ,
/* 33 */ 0x06B7 ,
/* 34 */ 0x06BA ,
/* 35 */ 0x06BB ,
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/* 36 */ VX_INVALID ,
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/* 37 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x000D ) ,
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/* 38 */ 0x006C ,
/* 39 */ 0x006D ,
/* 3A */ 0x006B ,
/* 3B */ 0x006A ,
/* 3C */ 0x0070 ,
/* 3D */ 0x006F ,
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/* 3E */ VX_INVALID ,
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/* 3F */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x000E ) ,
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/* 40 */ 0x02AB ,
/* 41 */ 0x02AC ,
/* 42 */ 0x02B2 ,
/* 43 */ 0x02B1 ,
/* 44 */ 0x02B3 ,
/* 45 */ 0x02B4 ,
/* 46 */ 0x02AE ,
/* 47 */ 0x02AD ,
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/* 48 */ 0x00A7 ,
/* 49 */ 0x00A6 ,
/* 4A */ 0x00A8 ,
/* 4B */ 0x00AA ,
/* 4C */ 0x00A9 ,
/* 4D */ 0x00A2 ,
/* 4E */ 0x00A1 ,
/* 4F */ 0x00A3 ,
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/* 50 */ 0x04B4 ,
/* 51 */ 0x04B9 ,
/* 52 */ 0x04B3 ,
/* 53 */ 0x04AE ,
/* 54 */ 0x04AF ,
/* 55 */ 0x04B0 ,
/* 56 */ 0x04B1 ,
/* 57 */ 0x04B2 ,
/* 58 */ 0x0449 ,
/* 59 */ 0x0447 ,
/* 5A */ 0x0448 ,
/* 5B */ 0x0442 ,
/* 5C */ 0x043E ,
/* 5D */ 0x043D ,
/* 5E */ 0x043F ,
/* 5F */ 0x0441 ,
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/* 60 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0007 ) ,
/* 61 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0008 ) ,
/* 62 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0013 ) ,
/* 63 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0014 ) ,
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/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
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/* 68 */ 0x04B7 ,
/* 69 */ 0x02A4 ,
/* 6A */ 0x04AB ,
/* 6B */ 0x02A6 ,
/* 6C */ 0x02B5 ,
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/* 6D */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0009 ) ,
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/* 6E */ 0x039F ,
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/* 6F */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x000A ) ,
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/* 70 */ 0x02E8 ,
/* 71 */ 0x02E2 ,
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/* 72 */ 0x02CA ,
/* 73 */ 0x02DE ,
/* 74 */ 0x02CE ,
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/* 75 */ 0x02E1 ,
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/* 76 */ 0x02CB ,
/* 77 */ 0x02C7 ,
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/* 78 */ 0x02ED ,
/* 79 */ 0x02E6 ,
/* 7A */ 0x02EB ,
/* 7B */ 0x02E5 ,
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/* 7C */ 0x02D5 ,
/* 7D */ 0x02D3 ,
/* 7E */ 0x02D8 ,
/* 7F */ 0x02D1 ,
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/* 80 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0013 ) ,
/* 81 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0014 ) ,
/* 82 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0015 ) ,
/* 83 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0016 ) ,
/* 84 */ 0x055C ,
/* 85 */ 0x055D ,
/* 86 */ 0x06A8 ,
/* 87 */ 0x06A7 ,
/* 88 */ 0x0334 ,
/* 89 */ 0x0336 ,
/* 8A */ 0x0335 ,
/* 8B */ 0x0331 ,
/* 8C */ 0x031D ,
/* 8D */ 0x02F4 ,
/* 8E */ 0x031C ,
/* 8F */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0017 ) ,
/* 90 */ 0x06A9 ,
/* 91 */ 0x06AB ,
/* 92 */ 0x06AA ,
/* 93 */ 0x06A3 ,
/* 94 */ 0x06A2 ,
/* 95 */ 0x06A4 ,
/* 96 */ 0x06A6 ,
/* 97 */ 0x06A5 ,
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/* 98 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x000B ) ,
/* 99 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x000C ) ,
/* 9A */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x001D ) ,
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/* 9B */ 0x069D ,
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/* 9C */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x000D ) ,
/* 9D */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x000E ) ,
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/* 9E */ 0x04EF ,
/* 9F */ 0x02EF ,
/* A0 */ 0x031B ,
/* A1 */ 0x0320 ,
/* A2 */ 0x031F ,
/* A3 */ 0x031E ,
/* A4 */ 0x0367 ,
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/* A5 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x000F ) ,
/* A6 */ 0x0076 ,
/* A7 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0010 ) ,
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/* A8 */ 0x055E ,
/* A9 */ 0x055B ,
/* AA */ 0x053D ,
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/* AB */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0011 ) ,
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/* AC */ 0x0300 ,
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/* AD */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0012 ) ,
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/* AE */ 0x0501 ,
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/* AF */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0013 ) ,
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/* B0 */ 0x0317 ,
/* B1 */ 0x031A ,
/* B2 */ 0x0318 ,
/* B3 */ 0x0319 ,
/* B4 */ 0x0321 ,
/* B5 */ 0x032C ,
/* B6 */ 0x032B ,
/* B7 */ 0x032A ,
/* B8 */ 0x032D ,
/* B9 */ 0x0330 ,
/* BA */ 0x032F ,
/* BB */ 0x032E ,
/* BC */ 0x0329 ,
/* BD */ 0x0324 ,
/* BE */ 0x0323 ,
/* BF */ 0x0322 ,
/* C0 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0018 ) ,
/* C1 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0019 ) ,
/* C2 */ 0x04D9 ,
/* C3 */ 0x04D8 ,
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/* C4 */ NODE ( VXOpcodeTreeNodeType : : VEX , 0x0000 ) ,
/* C5 */ NODE ( VXOpcodeTreeNodeType : : VEX , 0x0001 ) ,
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/* C6 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x001E ) ,
/* C7 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x001F ) ,
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/* C8 */ 0x00B4 ,
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/* C9 */ 0x02F5 ,
/* CA */ 0x04DA ,
/* CB */ 0x04DB ,
/* CC */ 0x02BB ,
/* CD */ 0x02B9 ,
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/* CE */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0027 ) ,
/* CF */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0017 ) ,
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/* D0 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0020 ) ,
/* D1 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0021 ) ,
/* D2 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0022 ) ,
/* D3 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0023 ) ,
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/* D4 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0028 ) ,
/* D5 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0029 ) ,
/* D6 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x002A ) ,
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/* D7 */ 0x06B2 ,
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/* D8 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0015 ) ,
/* D9 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0016 ) ,
/* DA */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0017 ) ,
/* DB */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0018 ) ,
/* DC */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0019 ) ,
/* DD */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x001A ) ,
/* DE */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x001B ) ,
/* DF */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x001C ) ,
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/* E0 */ 0x0306 ,
/* E1 */ 0x0305 ,
/* E2 */ 0x0304 ,
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/* E3 */ NODE ( VXOpcodeTreeNodeType : : ADDRESS_SIZE , 0x0000 ) ,
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/* E4 */ 0x02A9 ,
/* E5 */ 0x02AA ,
/* E6 */ 0x039D ,
/* E7 */ 0x039E ,
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/* E8 */ 0x004E ,
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/* E9 */ 0x02DB ,
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/* EA */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x002B ) ,
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/* EB */ 0x02DD ,
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/* EC */ 0x02A7 ,
/* ED */ 0x02A8 ,
/* EE */ 0x039B ,
/* EF */ 0x039C ,
/* F0 */ 0x02FF ,
/* F1 */ 0x02BA ,
/* F2 */ 0x04D7 ,
/* F3 */ 0x04D6 ,
/* F4 */ 0x029D ,
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/* F5 */ 0x0059 ,
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/* F6 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x002C ) ,
/* F7 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x002D ) ,
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/* F8 */ 0x0053 ,
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/* F9 */ 0x0538 ,
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/* FA */ 0x0057 ,
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/* FB */ 0x053B ,
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/* FC */ 0x0054 ,
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/* FD */ 0x0539 ,
/* FE */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x002E ) ,
/* FF */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x002F ) ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0000 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0000 ) ,
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/* 02 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0003 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0004 ) ,
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/* 04 */ VX_INVALID ,
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/* 05 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0005 ) ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0006 ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0007 ) ,
/* 08 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0008 ) ,
/* 09 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0009 ) ,
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/* 0A */ VX_INVALID ,
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/* 0B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x000A ) ,
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/* 0C */ VX_INVALID ,
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/* 0D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x000B ) ,
/* 0E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x000C ) ,
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/* 0F */ NODE ( VXOpcodeTreeNodeType : : AMD3DNOW , 0x0000 ) ,
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/* 10 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x000D ) ,
/* 11 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x000E ) ,
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/* 12 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0001 ) ,
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/* 13 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0011 ) ,
/* 14 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0012 ) ,
/* 15 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0013 ) ,
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/* 16 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0002 ) ,
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/* 17 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0016 ) ,
/* 18 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0017 ) ,
/* 19 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0018 ) ,
/* 1A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0019 ) ,
/* 1B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x001A ) ,
/* 1C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x001B ) ,
/* 1D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x001C ) ,
/* 1E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x001D ) ,
/* 1F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x001E ) ,
/* 20 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x001F ) ,
/* 21 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0020 ) ,
/* 22 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0021 ) ,
/* 23 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0022 ) ,
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/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
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/* 28 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0023 ) ,
/* 29 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0024 ) ,
/* 2A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0025 ) ,
/* 2B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0026 ) ,
/* 2C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0027 ) ,
/* 2D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0028 ) ,
/* 2E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0029 ) ,
/* 2F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x002A ) ,
/* 30 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x002B ) ,
/* 31 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x002C ) ,
/* 32 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x002D ) ,
/* 33 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x002E ) ,
/* 34 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x002F ) ,
/* 35 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0030 ) ,
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/* 36 */ VX_INVALID ,
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/* 37 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0031 ) ,
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/* 38 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0002 ) ,
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/* 39 */ VX_INVALID ,
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/* 3A */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0003 ) ,
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/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
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/* 40 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0081 ) ,
/* 41 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0082 ) ,
/* 42 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0083 ) ,
/* 43 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0084 ) ,
/* 44 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0085 ) ,
/* 45 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0086 ) ,
/* 46 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0087 ) ,
/* 47 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0088 ) ,
/* 48 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0089 ) ,
/* 49 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x008A ) ,
/* 4A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x008B ) ,
/* 4B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x008C ) ,
/* 4C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x008D ) ,
/* 4D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x008E ) ,
/* 4E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x008F ) ,
/* 4F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0090 ) ,
/* 50 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0091 ) ,
/* 51 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0092 ) ,
/* 52 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0093 ) ,
/* 53 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0094 ) ,
/* 54 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0095 ) ,
/* 55 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0096 ) ,
/* 56 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0097 ) ,
/* 57 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0098 ) ,
/* 58 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0099 ) ,
/* 59 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x009A ) ,
/* 5A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x009B ) ,
/* 5B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x009C ) ,
/* 5C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x009D ) ,
/* 5D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x009E ) ,
/* 5E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x009F ) ,
/* 5F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A0 ) ,
/* 60 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A1 ) ,
/* 61 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A2 ) ,
/* 62 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A3 ) ,
/* 63 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A4 ) ,
/* 64 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A5 ) ,
/* 65 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A6 ) ,
/* 66 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A7 ) ,
/* 67 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A8 ) ,
/* 68 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00A9 ) ,
/* 69 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00AA ) ,
/* 6A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00AB ) ,
/* 6B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00AC ) ,
/* 6C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00AD ) ,
/* 6D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00AE ) ,
/* 6E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00AF ) ,
/* 6F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B0 ) ,
/* 70 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B1 ) ,
/* 71 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B2 ) ,
/* 72 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B3 ) ,
/* 73 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B4 ) ,
/* 74 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B5 ) ,
/* 75 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B6 ) ,
/* 76 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B7 ) ,
/* 77 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B8 ) ,
/* 78 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00B9 ) ,
/* 79 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00BA ) ,
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/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
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/* 7C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00BB ) ,
/* 7D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00BC ) ,
/* 7E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00BD ) ,
/* 7F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00BE ) ,
/* 80 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00BF ) ,
/* 81 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C0 ) ,
/* 82 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C1 ) ,
/* 83 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C2 ) ,
/* 84 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C3 ) ,
/* 85 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C4 ) ,
/* 86 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C5 ) ,
/* 87 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C6 ) ,
/* 88 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C7 ) ,
/* 89 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C8 ) ,
/* 8A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00C9 ) ,
/* 8B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00CA ) ,
/* 8C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00CB ) ,
/* 8D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00CC ) ,
/* 8E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00CD ) ,
/* 8F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00CE ) ,
/* 90 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00CF ) ,
/* 91 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D0 ) ,
/* 92 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D1 ) ,
/* 93 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D2 ) ,
/* 94 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D3 ) ,
/* 95 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D4 ) ,
/* 96 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D5 ) ,
/* 97 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D6 ) ,
/* 98 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D7 ) ,
/* 99 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D8 ) ,
/* 9A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00D9 ) ,
/* 9B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00DA ) ,
/* 9C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00DB ) ,
/* 9D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00DC ) ,
/* 9E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00DD ) ,
/* 9F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00DE ) ,
/* A0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00DF ) ,
/* A1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E0 ) ,
/* A2 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E1 ) ,
/* A3 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E2 ) ,
/* A4 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E3 ) ,
/* A5 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E4 ) ,
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/* A6 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0003 ) ,
/* A7 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0004 ) ,
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/* A8 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E7 ) ,
/* A9 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E8 ) ,
/* AA */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E9 ) ,
/* AB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00EA ) ,
/* AC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00EB ) ,
/* AD */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00EC ) ,
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/* AE */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0005 ) ,
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/* AF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00EF ) ,
/* B0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F0 ) ,
/* B1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F1 ) ,
/* B2 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F2 ) ,
/* B3 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F3 ) ,
/* B4 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F4 ) ,
/* B5 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F5 ) ,
/* B6 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F6 ) ,
/* B7 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F7 ) ,
/* B8 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F8 ) ,
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/* B9 */ VX_INVALID ,
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/* BA */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00F9 ) ,
/* BB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00FA ) ,
/* BC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00FB ) ,
/* BD */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00FC ) ,
/* BE */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00FD ) ,
/* BF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00FE ) ,
/* C0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00FF ) ,
/* C1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0100 ) ,
/* C2 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0101 ) ,
/* C3 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0102 ) ,
/* C4 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0103 ) ,
/* C5 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0104 ) ,
/* C6 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0105 ) ,
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/* C7 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0006 ) ,
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/* C8 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0108 ) ,
/* C9 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0109 ) ,
/* CA */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x010A ) ,
/* CB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x010B ) ,
/* CC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x010C ) ,
/* CD */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x010D ) ,
/* CE */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x010E ) ,
/* CF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x010F ) ,
/* D0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0110 ) ,
/* D1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0111 ) ,
/* D2 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0112 ) ,
/* D3 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0113 ) ,
/* D4 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0114 ) ,
/* D5 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0115 ) ,
/* D6 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0116 ) ,
/* D7 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0117 ) ,
/* D8 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0118 ) ,
/* D9 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0119 ) ,
/* DA */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x011A ) ,
/* DB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x011B ) ,
/* DC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x011C ) ,
/* DD */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x011D ) ,
/* DE */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x011E ) ,
/* DF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x011F ) ,
/* E0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0120 ) ,
/* E1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0121 ) ,
/* E2 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0122 ) ,
/* E3 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0123 ) ,
/* E4 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0124 ) ,
/* E5 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0125 ) ,
/* E6 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0126 ) ,
/* E7 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0127 ) ,
/* E8 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0128 ) ,
/* E9 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0129 ) ,
/* EA */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x012A ) ,
/* EB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x012B ) ,
/* EC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x012C ) ,
/* ED */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x012D ) ,
/* EE */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x012E ) ,
/* EF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x012F ) ,
/* F0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0130 ) ,
/* F1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0131 ) ,
/* F2 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0132 ) ,
/* F3 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0133 ) ,
/* F4 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0134 ) ,
/* F5 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0135 ) ,
/* F6 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0136 ) ,
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/* F7 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0007 ) ,
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/* F8 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0138 ) ,
/* F9 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0139 ) ,
/* FA */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x013A ) ,
/* FB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x013B ) ,
/* FC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x013C ) ,
/* FD */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x013D ) ,
/* FE */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x013E ) ,
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/* FF */ VX_INVALID ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0032 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0033 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0034 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0035 ) ,
/* 04 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0036 ) ,
/* 05 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0037 ) ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0038 ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0039 ) ,
/* 08 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x003A ) ,
/* 09 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x003B ) ,
/* 0A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x003C ) ,
/* 0B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x003D ) ,
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/* 0C */ VX_INVALID ,
/* 0D */ VX_INVALID ,
/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
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/* 10 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x003E ) ,
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/* 11 */ VX_INVALID ,
/* 12 */ VX_INVALID ,
/* 13 */ VX_INVALID ,
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/* 14 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x003F ) ,
/* 15 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0040 ) ,
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/* 16 */ VX_INVALID ,
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/* 17 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0041 ) ,
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/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
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/* 1C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0042 ) ,
/* 1D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0043 ) ,
/* 1E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0044 ) ,
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/* 1F */ VX_INVALID ,
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/* 20 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0045 ) ,
/* 21 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0046 ) ,
/* 22 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0047 ) ,
/* 23 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0048 ) ,
/* 24 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0049 ) ,
/* 25 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x004A ) ,
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/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
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/* 28 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x004B ) ,
/* 29 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x004C ) ,
/* 2A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x004D ) ,
/* 2B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x004E ) ,
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/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
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/* 30 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x004F ) ,
/* 31 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0050 ) ,
/* 32 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0051 ) ,
/* 33 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0052 ) ,
/* 34 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0053 ) ,
/* 35 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0054 ) ,
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/* 36 */ VX_INVALID ,
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/* 37 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0055 ) ,
/* 38 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0056 ) ,
/* 39 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0057 ) ,
/* 3A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0058 ) ,
/* 3B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0059 ) ,
/* 3C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x005A ) ,
/* 3D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x005B ) ,
/* 3E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x005C ) ,
/* 3F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x005D ) ,
/* 40 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x005E ) ,
/* 41 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x005F ) ,
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/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
/* 51 */ VX_INVALID ,
/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
/* 58 */ VX_INVALID ,
/* 59 */ VX_INVALID ,
/* 5A */ VX_INVALID ,
/* 5B */ VX_INVALID ,
/* 5C */ VX_INVALID ,
/* 5D */ VX_INVALID ,
/* 5E */ VX_INVALID ,
/* 5F */ VX_INVALID ,
/* 60 */ VX_INVALID ,
/* 61 */ VX_INVALID ,
/* 62 */ VX_INVALID ,
/* 63 */ VX_INVALID ,
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
/* 70 */ VX_INVALID ,
/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
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/* 80 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0060 ) ,
/* 81 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0061 ) ,
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/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
/* C2 */ VX_INVALID ,
/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* DB */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0062 ) ,
/* DC */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0063 ) ,
/* DD */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0064 ) ,
/* DE */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0065 ) ,
/* DF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0066 ) ,
2015-03-16 06:28:54 +08:00
/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
/* E6 */ VX_INVALID ,
/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* F0 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0067 ) ,
/* F1 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0068 ) ,
2015-03-16 06:28:54 +08:00
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
} ,
{
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 08 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0069 ) ,
/* 09 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x006A ) ,
/* 0A */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x006B ) ,
/* 0B */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x006C ) ,
/* 0C */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x006D ) ,
/* 0D */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x006E ) ,
/* 0E */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x006F ) ,
/* 0F */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0070 ) ,
2015-03-16 06:28:54 +08:00
/* 10 */ VX_INVALID ,
/* 11 */ VX_INVALID ,
/* 12 */ VX_INVALID ,
/* 13 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 14 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0071 ) ,
/* 15 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0072 ) ,
/* 16 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0073 ) ,
/* 17 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0074 ) ,
2015-03-16 06:28:54 +08:00
/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 20 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0075 ) ,
/* 21 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0076 ) ,
/* 22 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0077 ) ,
2015-03-16 06:28:54 +08:00
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
/* 28 */ VX_INVALID ,
/* 29 */ VX_INVALID ,
/* 2A */ VX_INVALID ,
/* 2B */ VX_INVALID ,
/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 40 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0078 ) ,
/* 41 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0079 ) ,
/* 42 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x007A ) ,
2015-03-16 06:28:54 +08:00
/* 43 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 44 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x007B ) ,
2015-03-16 06:28:54 +08:00
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
/* 51 */ VX_INVALID ,
/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
/* 58 */ VX_INVALID ,
/* 59 */ VX_INVALID ,
/* 5A */ VX_INVALID ,
/* 5B */ VX_INVALID ,
/* 5C */ VX_INVALID ,
/* 5D */ VX_INVALID ,
/* 5E */ VX_INVALID ,
/* 5F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 60 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x007C ) ,
/* 61 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x007D ) ,
/* 62 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x007E ) ,
/* 63 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x007F ) ,
2015-03-16 06:28:54 +08:00
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
/* 70 */ VX_INVALID ,
/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
/* C2 */ VX_INVALID ,
/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
/* DB */ VX_INVALID ,
/* DC */ VX_INVALID ,
/* DD */ VX_INVALID ,
/* DE */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* DF */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0080 ) ,
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/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
/* E6 */ VX_INVALID ,
/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
/* F0 */ VX_INVALID ,
/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
} ,
{
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
/* 08 */ VX_INVALID ,
/* 09 */ VX_INVALID ,
/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
/* 0C */ VX_INVALID ,
/* 0D */ VX_INVALID ,
/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 10 */ 0x05E6 ,
/* 11 */ 0x05E5 ,
2014-10-25 05:11:16 +08:00
/* 12 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0008 ) ,
2014-10-27 21:10:22 +08:00
/* 13 */ 0x05CC ,
/* 14 */ 0x0698 ,
/* 15 */ 0x0696 ,
2014-10-25 05:11:16 +08:00
/* 16 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0009 ) ,
2014-10-27 21:10:22 +08:00
/* 17 */ 0x05C7 ,
2015-03-16 06:28:54 +08:00
/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
/* 20 */ VX_INVALID ,
/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 28 */ 0x05B8 ,
/* 29 */ 0x05B7 ,
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/* 2A */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 2B */ 0x05D2 ,
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/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 2E */ 0x0694 ,
/* 2F */ 0x0581 ,
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/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
/* 40 */ VX_INVALID ,
/* 41 */ VX_INVALID ,
/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 50 */ 0x05CE ,
/* 51 */ 0x0689 ,
/* 52 */ 0x0684 ,
/* 53 */ 0x067E ,
/* 54 */ 0x0575 ,
/* 55 */ 0x0573 ,
/* 56 */ 0x05F6 ,
/* 57 */ 0x069A ,
/* 58 */ 0x0567 ,
/* 59 */ 0x05EF ,
/* 5A */ 0x0587 ,
/* 5B */ 0x0583 ,
/* 5C */ 0x068E ,
/* 5D */ 0x05AF ,
/* 5E */ 0x0593 ,
/* 5F */ 0x05A9 ,
2015-03-16 06:28:54 +08:00
/* 60 */ VX_INVALID ,
/* 61 */ VX_INVALID ,
/* 62 */ VX_INVALID ,
/* 63 */ VX_INVALID ,
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
/* 70 */ VX_INVALID ,
/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
/* 77 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0000 ) ,
2015-03-16 06:28:54 +08:00
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
/* AE */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x000A ) ,
2015-03-16 06:28:54 +08:00
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* C2 */ 0x057D ,
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/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
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/* C6 */ 0x0687 ,
2015-03-16 06:28:54 +08:00
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
/* DB */ VX_INVALID ,
/* DC */ VX_INVALID ,
/* DD */ VX_INVALID ,
/* DE */ VX_INVALID ,
/* DF */ VX_INVALID ,
/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
/* E6 */ VX_INVALID ,
/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
/* F0 */ VX_INVALID ,
/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
} ,
{
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
/* 08 */ VX_INVALID ,
/* 09 */ VX_INVALID ,
/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
/* 0C */ VX_INVALID ,
/* 0D */ VX_INVALID ,
/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 10 */ 0x05E4 ,
/* 11 */ 0x05E3 ,
2014-10-25 05:11:16 +08:00
/* 12 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x000B ) ,
2014-10-27 21:10:22 +08:00
/* 13 */ 0x05CA ,
/* 14 */ 0x0697 ,
/* 15 */ 0x0695 ,
2014-10-25 05:11:16 +08:00
/* 16 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x000C ) ,
2014-10-27 21:10:22 +08:00
/* 17 */ 0x05C5 ,
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/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
/* 20 */ VX_INVALID ,
/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 28 */ 0x05B5 ,
/* 29 */ 0x05B6 ,
2015-03-16 06:28:54 +08:00
/* 2A */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 2B */ 0x05D1 ,
2015-03-16 06:28:54 +08:00
/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 2E */ 0x0693 ,
/* 2F */ 0x0580 ,
2015-03-16 06:28:54 +08:00
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
/* 40 */ VX_INVALID ,
/* 41 */ VX_INVALID ,
/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 50 */ 0x05CD ,
/* 51 */ 0x0688 ,
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/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 54 */ 0x0574 ,
/* 55 */ 0x0572 ,
/* 56 */ 0x05F5 ,
/* 57 */ 0x0699 ,
/* 58 */ 0x0566 ,
/* 59 */ 0x05EE ,
/* 5A */ 0x0585 ,
/* 5B */ 0x0586 ,
/* 5C */ 0x068D ,
/* 5D */ 0x05AE ,
/* 5E */ 0x0592 ,
/* 5F */ 0x05A8 ,
/* 60 */ 0x0679 ,
/* 61 */ 0x067C ,
/* 62 */ 0x067A ,
/* 63 */ 0x05FB ,
/* 64 */ 0x0614 ,
/* 65 */ 0x0617 ,
/* 66 */ 0x0615 ,
/* 67 */ 0x05FD ,
/* 68 */ 0x0675 ,
/* 69 */ 0x0678 ,
/* 6A */ 0x0676 ,
/* 6B */ 0x05FA ,
/* 6C */ 0x067B ,
/* 6D */ 0x0677 ,
2014-10-25 05:11:16 +08:00
/* 6E */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0014 ) ,
2014-10-27 21:10:22 +08:00
/* 6F */ 0x05BF ,
/* 70 */ 0x0654 ,
/* 71 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x001B ) ,
/* 72 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x001C ) ,
/* 73 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x001D ) ,
/* 74 */ 0x060E ,
/* 75 */ 0x0611 ,
/* 76 */ 0x060F ,
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/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
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/* 7C */ 0x059C ,
/* 7D */ 0x059E ,
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/* 7E */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0015 ) ,
2014-10-27 21:10:22 +08:00
/* 7F */ 0x05C0 ,
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/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* C2 */ 0x057C ,
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/* C3 */ VX_INVALID ,
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/* C4 */ 0x0630 ,
/* C5 */ 0x0623 ,
/* C6 */ 0x0686 ,
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/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* D0 */ 0x056A ,
/* D1 */ 0x066B ,
/* D2 */ 0x0665 ,
/* D3 */ 0x0669 ,
/* D4 */ 0x0600 ,
/* D5 */ 0x0650 ,
/* D6 */ 0x05D4 ,
2014-10-25 05:11:16 +08:00
/* D7 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0004 ) ,
2014-10-27 21:10:22 +08:00
/* D8 */ 0x0671 ,
/* D9 */ 0x0672 ,
/* DA */ 0x063C ,
/* DB */ 0x0607 ,
/* DC */ 0x0603 ,
/* DD */ 0x0604 ,
/* DE */ 0x0636 ,
/* DF */ 0x0608 ,
/* E0 */ 0x0609 ,
/* E1 */ 0x0663 ,
/* E2 */ 0x0662 ,
/* E3 */ 0x060A ,
/* E4 */ 0x064D ,
/* E5 */ 0x064E ,
/* E6 */ 0x058E ,
/* E7 */ 0x05CF ,
/* E8 */ 0x066F ,
/* E9 */ 0x0670 ,
/* EA */ 0x063B ,
/* EB */ 0x0651 ,
/* EC */ 0x0601 ,
/* ED */ 0x0602 ,
/* EE */ 0x0635 ,
/* EF */ 0x067D ,
2015-03-16 06:28:54 +08:00
/* F0 */ VX_INVALID ,
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/* F1 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0005 ) ,
/* F2 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0006 ) ,
/* F3 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0007 ) ,
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/* F4 */ VX_INVALID ,
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/* F5 */ 0x0632 ,
/* F6 */ 0x0652 ,
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/* F7 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x000D ) ,
2014-10-27 21:10:22 +08:00
/* F8 */ 0x066C ,
/* F9 */ 0x0673 ,
/* FA */ 0x066D ,
/* FB */ 0x066E ,
/* FC */ 0x05FE ,
/* FD */ 0x0605 ,
/* FE */ 0x05FF ,
2015-03-16 06:28:54 +08:00
/* FF */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0653 ,
/* 01 */ 0x0627 ,
/* 02 */ 0x0625 ,
/* 03 */ 0x0626 ,
/* 04 */ 0x0631 ,
/* 05 */ 0x062B ,
/* 06 */ 0x0629 ,
/* 07 */ 0x062A ,
/* 08 */ 0x0657 ,
/* 09 */ 0x0659 ,
/* 0A */ 0x0658 ,
/* 0B */ 0x064C ,
2014-10-25 05:11:16 +08:00
/* 0C */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0000 ) ,
/* 0D */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0001 ) ,
/* 0E */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0002 ) ,
/* 0F */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0003 ) ,
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/* 10 */ VX_INVALID ,
/* 11 */ VX_INVALID ,
/* 12 */ VX_INVALID ,
/* 13 */ VX_INVALID ,
/* 14 */ VX_INVALID ,
/* 15 */ VX_INVALID ,
/* 16 */ VX_INVALID ,
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/* 17 */ 0x0674 ,
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/* 18 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0004 ) ,
/* 19 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0005 ) ,
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/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
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/* 1C */ 0x05F7 ,
/* 1D */ 0x05F9 ,
/* 1E */ 0x05F8 ,
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/* 1F */ VX_INVALID ,
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/* 20 */ 0x0642 ,
/* 21 */ 0x0640 ,
/* 22 */ 0x0641 ,
/* 23 */ 0x0643 ,
/* 24 */ 0x0644 ,
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/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
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/* 28 */ 0x064B ,
/* 29 */ 0x0610 ,
/* 2A */ 0x05D0 ,
/* 2B */ 0x05FC ,
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/* 2C */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0006 ) ,
/* 2D */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0007 ) ,
/* 2E */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0008 ) ,
/* 2F */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0009 ) ,
2014-10-27 21:10:22 +08:00
/* 30 */ 0x0647 ,
/* 31 */ 0x0645 ,
/* 32 */ 0x0646 ,
/* 33 */ 0x0649 ,
/* 34 */ 0x064A ,
/* 35 */ 0x0648 ,
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/* 36 */ VX_INVALID ,
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/* 37 */ 0x0616 ,
/* 38 */ 0x0639 ,
/* 39 */ 0x063A ,
/* 3A */ 0x063E ,
/* 3B */ 0x063D ,
/* 3C */ 0x0633 ,
/* 3D */ 0x0634 ,
/* 3E */ 0x0638 ,
/* 3F */ 0x0637 ,
/* 40 */ 0x064F ,
/* 41 */ 0x0628 ,
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/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
/* 51 */ VX_INVALID ,
/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
/* 58 */ VX_INVALID ,
/* 59 */ VX_INVALID ,
/* 5A */ VX_INVALID ,
/* 5B */ VX_INVALID ,
/* 5C */ VX_INVALID ,
/* 5D */ VX_INVALID ,
/* 5E */ VX_INVALID ,
/* 5F */ VX_INVALID ,
/* 60 */ VX_INVALID ,
/* 61 */ VX_INVALID ,
/* 62 */ VX_INVALID ,
/* 63 */ VX_INVALID ,
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
/* 70 */ VX_INVALID ,
/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
/* C2 */ VX_INVALID ,
/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* DB */ 0x0570 ,
/* DC */ 0x056E ,
/* DD */ 0x056F ,
/* DE */ 0x056C ,
/* DF */ 0x056D ,
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/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
/* E6 */ VX_INVALID ,
/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
/* F0 */ VX_INVALID ,
/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
} ,
{
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
/* 04 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x000A ) ,
/* 05 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x000B ) ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x000C ) ,
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/* 07 */ VX_INVALID ,
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/* 08 */ 0x0681 ,
/* 09 */ 0x0680 ,
/* 0A */ 0x0683 ,
/* 0B */ 0x0682 ,
/* 0C */ 0x0577 ,
/* 0D */ 0x0576 ,
/* 0E */ 0x060C ,
/* 0F */ 0x0606 ,
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/* 10 */ VX_INVALID ,
/* 11 */ VX_INVALID ,
/* 12 */ VX_INVALID ,
/* 13 */ VX_INVALID ,
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/* 14 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x000D ) ,
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/* 15 */ 0x0624 ,
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/* 16 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0016 ) ,
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/* 17 */ 0x059B ,
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/* 18 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0011 ) ,
/* 19 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0012 ) ,
2015-03-16 06:28:54 +08:00
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
/* 20 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0013 ) ,
2014-10-27 21:10:22 +08:00
/* 21 */ 0x05A1 ,
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/* 22 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0025 ) ,
2015-03-16 06:28:54 +08:00
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
/* 28 */ VX_INVALID ,
/* 29 */ VX_INVALID ,
/* 2A */ VX_INVALID ,
/* 2B */ VX_INVALID ,
/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 40 */ 0x0597 ,
/* 41 */ 0x0596 ,
/* 42 */ 0x05E7 ,
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/* 43 */ VX_INVALID ,
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/* 44 */ 0x060D ,
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/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
/* 4A */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0016 ) ,
/* 4B */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0017 ) ,
/* 4C */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0018 ) ,
2015-03-16 06:28:54 +08:00
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
/* 51 */ VX_INVALID ,
/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
/* 58 */ VX_INVALID ,
/* 59 */ VX_INVALID ,
/* 5A */ VX_INVALID ,
/* 5B */ VX_INVALID ,
/* 5C */ VX_INVALID ,
/* 5D */ VX_INVALID ,
/* 5E */ VX_INVALID ,
/* 5F */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 60 */ 0x0613 ,
/* 61 */ 0x0612 ,
/* 62 */ 0x0619 ,
/* 63 */ 0x0618 ,
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/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
/* 70 */ VX_INVALID ,
/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
/* C2 */ VX_INVALID ,
/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
/* DB */ VX_INVALID ,
/* DC */ VX_INVALID ,
/* DD */ VX_INVALID ,
/* DE */ VX_INVALID ,
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/* DF */ 0x0571 ,
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/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
/* E6 */ VX_INVALID ,
/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
/* F0 */ VX_INVALID ,
/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
} ,
{
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
/* 08 */ VX_INVALID ,
/* 09 */ VX_INVALID ,
/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
/* 0C */ VX_INVALID ,
/* 0D */ VX_INVALID ,
/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
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/* 10 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x000E ) ,
/* 11 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x000F ) ,
/* 12 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0010 ) ,
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/* 13 */ VX_INVALID ,
/* 14 */ VX_INVALID ,
/* 15 */ VX_INVALID ,
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/* 16 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0011 ) ,
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/* 17 */ VX_INVALID ,
/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
/* 20 */ VX_INVALID ,
/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
/* 28 */ VX_INVALID ,
/* 29 */ VX_INVALID ,
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/* 2A */ 0x058B ,
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/* 2B */ VX_INVALID ,
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/* 2C */ 0x0591 ,
/* 2D */ 0x058D ,
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/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
/* 40 */ VX_INVALID ,
/* 41 */ VX_INVALID ,
/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
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/* 51 */ 0x068B ,
/* 52 */ 0x0685 ,
/* 53 */ 0x067F ,
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/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
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/* 58 */ 0x0569 ,
/* 59 */ 0x05F1 ,
/* 5A */ 0x058C ,
/* 5B */ 0x058F ,
/* 5C */ 0x0690 ,
/* 5D */ 0x05B1 ,
/* 5E */ 0x0595 ,
/* 5F */ 0x05AB ,
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/* 60 */ VX_INVALID ,
/* 61 */ VX_INVALID ,
/* 62 */ VX_INVALID ,
/* 63 */ VX_INVALID ,
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
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/* 6F */ 0x05C2 ,
/* 70 */ 0x0655 ,
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/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
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/* 7E */ 0x05D3 ,
/* 7F */ 0x05C1 ,
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/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
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/* C2 */ 0x057F ,
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/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
/* DB */ VX_INVALID ,
/* DC */ VX_INVALID ,
/* DD */ VX_INVALID ,
/* DE */ VX_INVALID ,
/* DF */ VX_INVALID ,
/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
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/* E6 */ 0x0582 ,
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/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
/* F0 */ VX_INVALID ,
/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
} ,
{
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
/* 08 */ VX_INVALID ,
/* 09 */ VX_INVALID ,
/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
/* 0C */ VX_INVALID ,
/* 0D */ VX_INVALID ,
/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
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/* 10 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0012 ) ,
/* 11 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0013 ) ,
/* 12 */ NODE ( VXOpcodeTreeNodeType : : MODRM_MOD , 0x0014 ) ,
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/* 13 */ VX_INVALID ,
/* 14 */ VX_INVALID ,
/* 15 */ VX_INVALID ,
/* 16 */ VX_INVALID ,
/* 17 */ VX_INVALID ,
/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
/* 20 */ VX_INVALID ,
/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
/* 28 */ VX_INVALID ,
/* 29 */ VX_INVALID ,
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/* 2A */ 0x058A ,
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/* 2B */ VX_INVALID ,
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/* 2C */ 0x0590 ,
/* 2D */ 0x0588 ,
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/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
/* 40 */ VX_INVALID ,
/* 41 */ VX_INVALID ,
/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
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/* 51 */ 0x068A ,
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/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
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/* 58 */ 0x0568 ,
/* 59 */ 0x05F0 ,
/* 5A */ 0x0589 ,
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/* 5B */ VX_INVALID ,
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/* 5C */ 0x068F ,
/* 5D */ 0x05B0 ,
/* 5E */ 0x0594 ,
/* 5F */ 0x05AA ,
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/* 60 */ VX_INVALID ,
/* 61 */ VX_INVALID ,
/* 62 */ VX_INVALID ,
/* 63 */ VX_INVALID ,
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
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/* 70 */ 0x0656 ,
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/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
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/* 7C */ 0x059D ,
/* 7D */ 0x059F ,
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/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
/* 8A */ VX_INVALID ,
/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
/* 8E */ VX_INVALID ,
/* 8F */ VX_INVALID ,
/* 90 */ VX_INVALID ,
/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
/* 94 */ VX_INVALID ,
/* 95 */ VX_INVALID ,
/* 96 */ VX_INVALID ,
/* 97 */ VX_INVALID ,
/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
/* 9A */ VX_INVALID ,
/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
/* 9E */ VX_INVALID ,
/* 9F */ VX_INVALID ,
/* A0 */ VX_INVALID ,
/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
/* A4 */ VX_INVALID ,
/* A5 */ VX_INVALID ,
/* A6 */ VX_INVALID ,
/* A7 */ VX_INVALID ,
/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
/* AA */ VX_INVALID ,
/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
/* AE */ VX_INVALID ,
/* AF */ VX_INVALID ,
/* B0 */ VX_INVALID ,
/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
/* B4 */ VX_INVALID ,
/* B5 */ VX_INVALID ,
/* B6 */ VX_INVALID ,
/* B7 */ VX_INVALID ,
/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
/* BB */ VX_INVALID ,
/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
/* BF */ VX_INVALID ,
/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
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/* C2 */ 0x057E ,
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/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
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/* D0 */ 0x056B ,
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/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
/* DB */ VX_INVALID ,
/* DC */ VX_INVALID ,
/* DD */ VX_INVALID ,
/* DE */ VX_INVALID ,
/* DF */ VX_INVALID ,
/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
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/* E6 */ 0x0584 ,
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/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
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/* F0 */ 0x05A2 ,
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/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeModrmMod [ ] [ 2 ] =
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{
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0001 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0002 ) ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x000F ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0010 ) ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0014 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0015 ) ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E5 ) ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00E6 ) ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00ED ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x00EE ) ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0106 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0107 ) ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : MANDATORY , 0x0137 ) ,
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} ,
{
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/* 00 */ 0x05CB ,
/* 01 */ 0x05C3 ,
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} ,
{
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/* 00 */ 0x05C6 ,
/* 01 */ 0x05C8 ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x001A ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05C9 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05C4 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05A3 ,
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} ,
{
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/* 00 */ 0x05E2 ,
/* 01 */ 0x05DF ,
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} ,
{
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/* 00 */ 0x05E0 ,
/* 01 */ 0x05E1 ,
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} ,
{
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/* 00 */ 0x05DE ,
/* 01 */ 0x05DD ,
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} ,
{
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/* 00 */ 0x05DB ,
/* 01 */ 0x05DC ,
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} ,
{
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/* 00 */ 0x05DA ,
/* 01 */ 0x05D9 ,
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} ,
{
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/* 00 */ 0x05D8 ,
/* 01 */ 0x05D7 ,
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} ,
{
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/* 00 */ 0x05BE ,
/* 01 */ 0x05BD ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0024 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0000 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0025 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0001 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0026 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0002 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0027 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0003 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0028 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0004 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0029 ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0005 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x002A ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0006 ) ,
} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x002B ) ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : X87 , 0x0007 ) ,
} ,
} ;
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const VXOpcodeTreeNode optreeModrmReg [ ] [ 8 ] =
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{
{
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/* 00 */ 0x0531 ,
/* 01 */ 0x0541 ,
/* 02 */ 0x02FC ,
/* 03 */ 0x0309 ,
/* 04 */ 0x0598 ,
/* 05 */ 0x0599 ,
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/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0516 ,
/* 01 */ 0x052F ,
/* 02 */ 0x02F9 ,
/* 03 */ 0x02FB ,
/* 04 */ 0x0533 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x02FE ,
/* 07 */ 0x02C0 ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0000 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0001 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0002 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0003 ) ,
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/* 04 */ 0x0532 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x02FD ,
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/* 07 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0004 ) ,
} ,
{
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/* 00 */ 0x0455 ,
/* 01 */ 0x0456 ,
/* 02 */ 0x0457 ,
/* 03 */ 0x0458 ,
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/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x0486 ,
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/* 03 */ VX_INVALID ,
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/* 04 */ 0x0479 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x0470 ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x0485 ,
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/* 03 */ VX_INVALID ,
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/* 04 */ 0x0478 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x0473 ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x047E ,
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/* 03 */ VX_INVALID ,
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/* 04 */ 0x0475 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x0468 ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x047C ,
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/* 03 */ VX_INVALID ,
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/* 04 */ 0x0476 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x046A ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x0482 ,
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/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ 0x046D ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x0481 ,
/* 03 */ 0x0480 ,
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/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ 0x046C ,
/* 07 */ 0x046B ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0005 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0006 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0007 ) ,
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/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0008 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x0009 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x000A ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x000B ) ,
/* 04 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x000C ) ,
/* 05 */ NODE ( VXOpcodeTreeNodeType : : MODRM_RM , 0x000D ) ,
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/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0296 ,
/* 01 */ 0x0295 ,
/* 02 */ 0x02F2 ,
/* 03 */ 0x053C ,
/* 04 */ 0x06C0 ,
/* 05 */ 0x06BF ,
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/* 06 */ VX_INVALID ,
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/* 07 */ 0x0055 ,
} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
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/* 05 */ 0x02F7 ,
/* 06 */ 0x0310 ,
/* 07 */ 0x0515 ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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/* 04 */ 0x0043 ,
/* 05 */ 0x0049 ,
/* 06 */ 0x0047 ,
/* 07 */ 0x0045 ,
} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0006 ) ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0015 ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0016 ) ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0017 ) ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0018 ) ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ 0x04D3 ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x000F ,
/* 01 */ 0x0392 ,
/* 02 */ 0x0005 ,
/* 03 */ 0x04FF ,
/* 04 */ 0x0028 ,
/* 05 */ 0x0544 ,
/* 06 */ 0x06BC ,
/* 07 */ 0x006E ,
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} ,
{
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/* 00 */ 0x0013 ,
/* 01 */ 0x0391 ,
/* 02 */ 0x0009 ,
/* 03 */ 0x0500 ,
/* 04 */ 0x0029 ,
/* 05 */ 0x0543 ,
/* 06 */ 0x06B5 ,
/* 07 */ 0x0072 ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0015 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0016 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0017 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0018 ) ,
/* 04 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0019 ) ,
/* 05 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x001A ) ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x001B ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x001C ) ,
} ,
{
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/* 00 */ 0x0012 ,
/* 01 */ 0x0397 ,
/* 02 */ 0x0008 ,
/* 03 */ 0x04FD ,
/* 04 */ 0x002B ,
/* 05 */ 0x0545 ,
/* 06 */ 0x06B4 ,
/* 07 */ 0x0071 ,
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} ,
{
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/* 00 */ 0x0440 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04DE ,
/* 01 */ 0x04E6 ,
/* 02 */ 0x04C6 ,
/* 03 */ 0x04D0 ,
/* 04 */ 0x0517 ,
/* 05 */ 0x0526 ,
/* 06 */ 0x051D ,
/* 07 */ 0x04F3 ,
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} ,
{
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/* 00 */ 0x04DF ,
/* 01 */ 0x04E7 ,
/* 02 */ 0x04C7 ,
/* 03 */ 0x04CE ,
/* 04 */ 0x051C ,
/* 05 */ 0x0528 ,
/* 06 */ 0x051E ,
/* 07 */ 0x04F6 ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x068C ,
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/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x066A ,
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/* 03 */ VX_INVALID ,
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/* 04 */ 0x0664 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0001 ) ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x0666 ,
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/* 03 */ VX_INVALID ,
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/* 04 */ 0x0661 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0002 ) ,
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/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
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/* 02 */ 0x0668 ,
/* 03 */ 0x0667 ,
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/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
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/* 06 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0003 ) ,
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/* 07 */ 0x065C ,
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} ,
{
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/* 00 */ 0x0333 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0332 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04DD ,
/* 01 */ 0x04E5 ,
/* 02 */ 0x04C8 ,
/* 03 */ 0x04CD ,
/* 04 */ 0x0522 ,
/* 05 */ 0x0527 ,
/* 06 */ 0x051F ,
/* 07 */ 0x04F1 ,
} ,
{
/* 00 */ 0x04DC ,
/* 01 */ 0x04E2 ,
/* 02 */ 0x04C5 ,
/* 03 */ 0x04CF ,
/* 04 */ 0x0520 ,
/* 05 */ 0x052A ,
/* 06 */ 0x0519 ,
/* 07 */ 0x04F4 ,
} ,
{
/* 00 */ 0x04E1 ,
/* 01 */ 0x04E3 ,
/* 02 */ 0x04C3 ,
/* 03 */ 0x04CC ,
/* 04 */ 0x0521 ,
/* 05 */ 0x0529 ,
/* 06 */ 0x051A ,
/* 07 */ 0x04F2 ,
} ,
{
/* 00 */ 0x04E0 ,
/* 01 */ 0x04E4 ,
/* 02 */ 0x04C4 ,
/* 03 */ 0x04CB ,
/* 04 */ 0x0518 ,
/* 05 */ 0x0525 ,
/* 06 */ 0x051B ,
/* 07 */ 0x04F5 ,
} ,
{
/* 00 */ 0x00BB ,
/* 01 */ 0x01CF ,
/* 02 */ 0x0119 ,
/* 03 */ 0x013D ,
/* 04 */ 0x022C ,
/* 05 */ 0x0245 ,
/* 06 */ 0x0166 ,
/* 07 */ 0x0171 ,
} ,
{
/* 00 */ 0x01BC ,
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/* 01 */ VX_INVALID ,
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/* 02 */ 0x01FF ,
/* 03 */ 0x020B ,
/* 04 */ 0x01C3 ,
/* 05 */ 0x01C2 ,
/* 06 */ 0x01EB ,
/* 07 */ 0x01EA ,
} ,
{
/* 00 */ 0x019A ,
/* 01 */ 0x01A8 ,
/* 02 */ 0x019C ,
/* 03 */ 0x019F ,
/* 04 */ 0x01B3 ,
/* 05 */ 0x01B5 ,
/* 06 */ 0x01A1 ,
/* 07 */ 0x01A3 ,
} ,
{
/* 00 */ 0x01A4 ,
/* 01 */ 0x01B1 ,
/* 02 */ 0x01AB ,
/* 03 */ 0x01AD ,
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/* 04 */ VX_INVALID ,
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/* 05 */ 0x01BA ,
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/* 06 */ VX_INVALID ,
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/* 07 */ 0x020A ,
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} ,
{
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/* 00 */ 0x00BA ,
/* 01 */ 0x01D2 ,
/* 02 */ 0x0118 ,
/* 03 */ 0x013E ,
/* 04 */ 0x022B ,
/* 05 */ 0x0243 ,
/* 06 */ 0x0158 ,
/* 07 */ 0x017A ,
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} ,
{
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/* 00 */ 0x01BB ,
/* 01 */ 0x01AF ,
/* 02 */ 0x01FE ,
/* 03 */ 0x0209 ,
/* 04 */ 0x01F3 ,
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/* 05 */ VX_INVALID ,
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/* 06 */ 0x01E8 ,
/* 07 */ 0x01ED ,
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} ,
{
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/* 00 */ 0x019B ,
/* 01 */ 0x01A7 ,
/* 02 */ 0x019D ,
/* 03 */ 0x019E ,
/* 04 */ 0x01B2 ,
/* 05 */ 0x01B4 ,
/* 06 */ 0x01A0 ,
/* 07 */ 0x01A2 ,
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} ,
{
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/* 00 */ 0x01A6 ,
/* 01 */ 0x01B0 ,
/* 02 */ 0x01AA ,
/* 03 */ 0x01AE ,
/* 04 */ 0x00D2 ,
/* 05 */ 0x01A5 ,
/* 06 */ 0x00D3 ,
/* 07 */ 0x01AC ,
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} ,
{
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/* 00 */ 0x0557 ,
/* 01 */ 0x0558 ,
/* 02 */ 0x038E ,
/* 03 */ 0x0385 ,
/* 04 */ 0x037E ,
/* 05 */ 0x02A5 ,
/* 06 */ 0x00AC ,
/* 07 */ 0x02A0 ,
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} ,
{
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/* 00 */ 0x0559 ,
/* 01 */ 0x055A ,
/* 02 */ 0x038D ,
/* 03 */ 0x0384 ,
/* 04 */ 0x037D ,
/* 05 */ 0x02A3 ,
/* 06 */ 0x00AB ,
/* 07 */ 0x02A1 ,
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} ,
{
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/* 00 */ 0x02AF ,
/* 01 */ 0x00A4 ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02B0 ,
/* 01 */ 0x00A5 ,
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/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x002C ) ,
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/* 03 */ 0x004C ,
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/* 04 */ 0x02D9 ,
/* 05 */ 0x02DA ,
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/* 06 */ 0x04B8 ,
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/* 07 */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeModrmRm [ ] [ 8 ] =
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{
{
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/* 00 */ VX_INVALID ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0000 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0001 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0002 ) ,
/* 04 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0003 ) ,
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/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0315 ,
/* 01 */ 0x0383 ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06B1 ,
/* 01 */ 0x06C1 ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0004 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0005 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0006 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0007 ) ,
/* 04 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0008 ) ,
/* 05 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0009 ) ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x000A ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x000B ) ,
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} ,
{
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/* 00 */ 0x0550 ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x000C ) ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0316 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06C2 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06C3 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06C4 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06AF ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06AC ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06AE ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06AD ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06B0 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeMandatory [ ] [ 4 ] =
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{
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0000 ) ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0001 ) ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0002 ) ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02F0 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0307 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0551 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0058 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0556 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02BD ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x069E ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0561 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0454 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0189 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0379 ,
/* 01 */ 0x0368 ,
/* 02 */ 0x0371 ,
/* 03 */ 0x0377 ,
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} ,
{
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/* 00 */ 0x0378 ,
/* 01 */ 0x036A ,
/* 02 */ 0x0370 ,
/* 03 */ 0x0376 ,
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} ,
{
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/* 00 */ 0x0355 ,
/* 01 */ 0x0345 ,
/* 02 */ 0x036D ,
/* 03 */ 0x0353 ,
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} ,
{
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/* 00 */ 0x034C ,
/* 01 */ 0x0346 ,
/* 02 */ 0x036E ,
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/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0354 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0352 ,
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} ,
{
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/* 00 */ 0x0565 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0564 ,
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} ,
{
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/* 00 */ 0x0563 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0562 ,
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} ,
{
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/* 00 */ 0x0350 ,
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/* 01 */ VX_INVALID ,
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/* 02 */ 0x036B ,
/* 03 */ 0x034E ,
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} ,
{
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/* 00 */ 0x0351 ,
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/* 01 */ VX_INVALID ,
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/* 02 */ 0x036C ,
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/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x034F ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x034D ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0003 ) ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x038A ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x038B ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x038C ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0389 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0386 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0387 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0388 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0325 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0328 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0327 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0326 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x033A ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0338 ,
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} ,
{
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/* 00 */ 0x0339 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0337 ,
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} ,
{
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/* 00 */ 0x008D ,
/* 01 */ 0x0093 ,
/* 02 */ 0x0094 ,
/* 03 */ 0x008C ,
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} ,
{
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/* 00 */ 0x035C ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x035B ,
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} ,
{
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/* 00 */ 0x009A ,
/* 01 */ 0x009B ,
/* 02 */ 0x009C ,
/* 03 */ 0x0098 ,
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} ,
{
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/* 00 */ 0x0090 ,
/* 01 */ 0x0091 ,
/* 02 */ 0x0096 ,
/* 03 */ 0x008A ,
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} ,
{
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/* 00 */ 0x0560 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x055F ,
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} ,
{
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/* 00 */ 0x0082 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0081 ,
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} ,
{
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/* 00 */ 0x069F ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04D4 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04D1 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04D2 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0003 ) ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0004 ) ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x029A ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x045B ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x045C ,
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} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03FD ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03FE ,
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} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03FA ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03F9 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03FB ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03FC ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x040E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x040F ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0405 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0404 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0400 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0401 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0402 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0403 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0461 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0462 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0466 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0465 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0464 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0463 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0431 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0432 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03CA ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0037 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0036 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x049A ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03A3 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03A2 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03A6 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03A7 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03A4 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03A5 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0426 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0424 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0425 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0428 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0429 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0427 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0430 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03D1 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0359 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03AC ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x042C ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x042A ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x042B ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x042E ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x042F ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x042D ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03DA ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x041A ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x041B ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0421 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0420 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0412 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0413 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0419 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0418 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0438 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03FF ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0005 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0006 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0023 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0021 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0022 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x001F ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0020 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x033B ,
/* 01 */ 0x0086 ,
2015-03-16 06:28:54 +08:00
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x033C ,
/* 01 */ 0x0085 ,
2015-03-16 06:28:54 +08:00
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04E9 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04E8 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04EB ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04EA ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0035 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0034 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03CB ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03BF ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03C0 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03DF ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03E3 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0000 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x00B5 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0408 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x02B7 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0001 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x00B2 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x00B1 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x037C ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03CC ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03D5 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03D4 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03DE ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03DD ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0024 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0067 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0064 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x005C ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x005B ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x005E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0063 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x005D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x005A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0069 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0066 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0068 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0065 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0061 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0060 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0062 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x005F ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0357 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0356 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0535 ,
/* 01 */ 0x0536 ,
/* 02 */ 0x0537 ,
/* 03 */ 0x0534 ,
} ,
{
/* 00 */ 0x04ED ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x04EE ,
2015-03-16 06:28:54 +08:00
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04C9 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x04CA ,
2015-03-16 06:28:54 +08:00
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0032 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0031 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0030 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x002F ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x039A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0399 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x06BE ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x06BD ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x001A ,
/* 01 */ 0x001B ,
/* 02 */ 0x001C ,
/* 03 */ 0x0019 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0380 ,
/* 01 */ 0x0381 ,
/* 02 */ 0x0382 ,
/* 03 */ 0x037F ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x008F ,
/* 01 */ 0x0092 ,
/* 02 */ 0x0095 ,
/* 03 */ 0x008B ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0088 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x0099 ,
/* 03 */ 0x008E ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x054D ,
/* 01 */ 0x054E ,
/* 02 */ 0x054F ,
/* 03 */ 0x054C ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0312 ,
/* 01 */ 0x0313 ,
/* 02 */ 0x0314 ,
/* 03 */ 0x0311 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x00AE ,
/* 01 */ 0x00AF ,
/* 02 */ 0x00B0 ,
/* 03 */ 0x00AD ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x030D ,
/* 01 */ 0x030E ,
/* 02 */ 0x030F ,
/* 03 */ 0x030C ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04A2 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04A3 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04A7 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04A8 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04A5 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04A4 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03AA ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03AB ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03D7 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03D6 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03DC ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03DB ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03D8 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03D9 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03AD ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03AE ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x049B ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x049C ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04A1 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04A0 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x049E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x049D ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03A8 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03A9 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x04A6 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x049F ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0002 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0003 ) ,
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0363 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x034A ,
/* 03 */ 0x0348 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0460 ,
/* 01 */ 0x045F ,
/* 02 */ 0x045E ,
/* 03 */ 0x045D ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0004 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0005 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0006 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0007 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0008 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0009 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03CD ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03CE ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03D2 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03D3 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03D0 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03CF ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x00B3 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0013 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0014 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 01 */ 0x029C ,
2015-03-16 06:28:54 +08:00
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x029B ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 01 */ 0x029F ,
2015-03-16 06:28:54 +08:00
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x029E ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0004 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x035F ,
2014-10-25 05:11:16 +08:00
/* 03 */ NODE ( VXOpcodeTreeNodeType : : OPERAND_SIZE , 0x0005 ) ,
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0362 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x034B ,
/* 03 */ 0x0349 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02E9 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02E3 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02C9 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02DF ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02CF ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x02E0 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02CC ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02C8 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02EE ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02E7 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02EA ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02E4 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02D6 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02D4 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02D7 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-30 23:36:25 +08:00
/* 00 */ 0x02D2 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0512 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x050F ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0507 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0506 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0509 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x050E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0508 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0505 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0514 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0511 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0513 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0510 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x050C ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x050B ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x050D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x050A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04B5 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x044A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x0083 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0044 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0524 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0523 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x000A ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x000B ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04B6 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0444 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x04EC ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x004A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x052C ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x052B ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x000C ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x000D ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02A2 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x007C ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x007D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0308 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0048 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02F8 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x02FA ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x037B ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x037A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ 0x044D ,
2015-03-16 06:28:54 +08:00
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x000E ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0046 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0039 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x003A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0373 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0374 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x06A1 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x06A0 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0075 ,
/* 01 */ 0x0077 ,
/* 02 */ 0x007A ,
/* 03 */ 0x0074 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x035A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x040D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x040C ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03E4 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03E5 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x052E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x052D ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x000F ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0010 ) ,
/* 03 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0011 ) ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODRM_REG , 0x0012 ) ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x003F ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x003D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x0040 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x003C ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x003E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x003B ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x0042 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
/* 00 */ 0x0041 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 01 */ 0x001E ,
2015-03-16 06:28:54 +08:00
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x001D ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0487 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0488 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x047D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x047F ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0483 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0484 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03B3 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03B4 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0439 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x043A ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 01 */ 0x0347 ,
/* 02 */ 0x0366 ,
/* 03 */ 0x0361 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0422 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0423 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0494 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0493 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0496 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0495 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x041E ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x041F ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03C1 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03C2 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03BA ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03B9 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03BB ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03BC ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0417 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0416 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03C3 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03C4 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03C5 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03C6 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x047A ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x047B ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0477 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0474 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x03C8 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x03C9 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0434 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0435 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0436 ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0437 ,
2014-10-25 05:11:16 +08:00
} ,
{
2015-03-16 06:28:54 +08:00
/* 00 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 01 */ 0x0089 ,
/* 02 */ 0x0087 ,
/* 03 */ 0x0097 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x035D ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0358 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x048F ,
2015-03-16 06:28:54 +08:00
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
2014-10-27 21:10:22 +08:00
/* 03 */ 0x0490 ,
2014-10-25 05:11:16 +08:00
} ,
{
2014-10-27 21:10:22 +08:00
/* 00 */ 0x0492 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0491 ,
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} ,
{
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/* 00 */ 0x041C ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x041D ,
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} ,
{
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/* 00 */ 0x0453 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0452 ,
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} ,
{
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/* 00 */ 0x03B6 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x03B5 ,
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} ,
{
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/* 00 */ 0x03B8 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x03B7 ,
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} ,
{
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/* 00 */ 0x0414 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0415 ,
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} ,
{
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/* 00 */ 0x04C1 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x04C2 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x02F1 ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0472 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0471 ,
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} ,
{
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/* 00 */ 0x0469 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0467 ,
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} ,
{
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/* 00 */ 0x046E ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x046F ,
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} ,
{
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/* 00 */ 0x043B ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x043C ,
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} ,
{
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/* 00 */ 0x0411 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0410 ,
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} ,
{
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/* 00 */ 0x045A ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0459 ,
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} ,
{
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/* 00 */ 0x030B ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x030A ,
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} ,
{
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/* 00 */ 0x0489 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x048A ,
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} ,
{
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/* 00 */ 0x0498 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x0497 ,
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} ,
{
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/* 00 */ 0x048B ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x048C ,
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} ,
{
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/* 00 */ 0x048D ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x048E ,
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} ,
{
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/* 00 */ 0x03AF ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x03B0 ,
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} ,
{
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/* 00 */ 0x03BE ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x03BD ,
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} ,
{
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/* 00 */ 0x03B1 ,
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/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
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/* 03 */ 0x03B2 ,
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} ,
} ;
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const VXOpcodeTreeNode optreeX87 [ ] [ 64 ] =
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{
{
/* 00 */ 0x00BC ,
/* 01 */ 0x00BF ,
/* 02 */ 0x00C2 ,
/* 03 */ 0x00C1 ,
/* 04 */ 0x00C0 ,
/* 05 */ 0x00C5 ,
/* 06 */ 0x00C3 ,
/* 07 */ 0x00C4 ,
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/* 08 */ 0x01CE ,
/* 09 */ 0x01CD ,
/* 0A */ 0x01D9 ,
/* 0B */ 0x01DA ,
/* 0C */ 0x01DB ,
/* 0D */ 0x01D6 ,
/* 0E */ 0x01D7 ,
/* 0F */ 0x01D8 ,
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/* 10 */ 0x011A ,
/* 11 */ 0x011C ,
/* 12 */ 0x011B ,
/* 13 */ 0x0117 ,
/* 14 */ 0x0116 ,
/* 15 */ 0x011D ,
/* 16 */ 0x011F ,
/* 17 */ 0x011E ,
/* 18 */ 0x013A ,
/* 19 */ 0x0141 ,
/* 1A */ 0x013C ,
/* 1B */ 0x0138 ,
/* 1C */ 0x013B ,
/* 1D */ 0x0140 ,
/* 1E */ 0x013F ,
/* 1F */ 0x0139 ,
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/* 20 */ 0x022E ,
/* 21 */ 0x0226 ,
/* 22 */ 0x0229 ,
/* 23 */ 0x0232 ,
/* 24 */ 0x0231 ,
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/* 25 */ 0x022D ,
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/* 26 */ 0x022A ,
/* 27 */ 0x0227 ,
/* 28 */ 0x0246 ,
/* 29 */ 0x024B ,
/* 2A */ 0x024C ,
/* 2B */ 0x024A ,
/* 2C */ 0x0248 ,
/* 2D */ 0x0249 ,
/* 2E */ 0x0250 ,
/* 2F */ 0x0251 ,
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/* 30 */ 0x0161 ,
/* 31 */ 0x0162 ,
/* 32 */ 0x0155 ,
/* 33 */ 0x015A ,
/* 34 */ 0x0159 ,
/* 35 */ 0x0156 ,
/* 36 */ 0x0157 ,
/* 37 */ 0x0163 ,
/* 38 */ 0x0172 ,
/* 39 */ 0x016F ,
/* 3A */ 0x0170 ,
/* 3B */ 0x0173 ,
/* 3C */ 0x0176 ,
/* 3D */ 0x0177 ,
/* 3E */ 0x0174 ,
/* 3F */ 0x0175 ,
} ,
{
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/* 00 */ 0x01BD ,
/* 01 */ 0x01C0 ,
/* 02 */ 0x01BF ,
/* 03 */ 0x01BE ,
/* 04 */ 0x01B7 ,
/* 05 */ 0x01B6 ,
/* 06 */ 0x01B9 ,
/* 07 */ 0x01B8 ,
/* 08 */ 0x0281 ,
/* 09 */ 0x0282 ,
/* 0A */ 0x0283 ,
/* 0B */ 0x0280 ,
/* 0C */ 0x027D ,
/* 0D */ 0x027E ,
/* 0E */ 0x027F ,
/* 0F */ 0x0284 ,
/* 10 */ 0x01E7 ,
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/* 11 */ VX_INVALID ,
/* 12 */ VX_INVALID ,
/* 13 */ VX_INVALID ,
/* 14 */ VX_INVALID ,
/* 15 */ VX_INVALID ,
/* 16 */ VX_INVALID ,
/* 17 */ VX_INVALID ,
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/* 18 */ 0x0213 ,
/* 19 */ 0x0212 ,
/* 1A */ 0x0215 ,
/* 1B */ 0x0214 ,
/* 1C */ 0x020F ,
/* 1D */ 0x020E ,
/* 1E */ 0x0211 ,
/* 1F */ 0x0210 ,
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/* 20 */ 0x00D4 ,
/* 21 */ 0x00B7 ,
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/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
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/* 24 */ 0x025A ,
/* 25 */ 0x027C ,
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/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
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/* 28 */ 0x01C1 ,
/* 29 */ 0x01C5 ,
/* 2A */ 0x01C4 ,
/* 2B */ 0x01C8 ,
/* 2C */ 0x01C6 ,
/* 2D */ 0x01C7 ,
/* 2E */ 0x01C9 ,
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/* 2F */ VX_INVALID ,
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/* 30 */ 0x00B6 ,
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/* 31 */ 0x0298 ,
/* 32 */ 0x01F1 ,
/* 33 */ 0x01EE ,
/* 34 */ 0x0297 ,
/* 35 */ 0x01F0 ,
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/* 36 */ 0x0154 ,
/* 37 */ 0x01A9 ,
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/* 38 */ 0x01EF ,
/* 39 */ 0x0299 ,
/* 3A */ 0x01F8 ,
/* 3B */ 0x01F7 ,
/* 3C */ 0x01F2 ,
/* 3D */ 0x01F5 ,
/* 3E */ 0x01F6 ,
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/* 3F */ 0x0153 ,
} ,
{
/* 00 */ 0x00D9 ,
/* 01 */ 0x00DA ,
/* 02 */ 0x00DB ,
/* 03 */ 0x00D6 ,
/* 04 */ 0x00D7 ,
/* 05 */ 0x00D8 ,
/* 06 */ 0x00DD ,
/* 07 */ 0x00DC ,
/* 08 */ 0x00E6 ,
/* 09 */ 0x00E7 ,
/* 0A */ 0x00E8 ,
/* 0B */ 0x00EC ,
/* 0C */ 0x00ED ,
/* 0D */ 0x00EB ,
/* 0E */ 0x00E9 ,
/* 0F */ 0x00EA ,
/* 10 */ 0x00E4 ,
/* 11 */ 0x00E5 ,
/* 12 */ 0x00E2 ,
/* 13 */ 0x00E3 ,
/* 14 */ 0x00DF ,
/* 15 */ 0x00DE ,
/* 16 */ 0x00E0 ,
/* 17 */ 0x00E1 ,
/* 18 */ 0x0113 ,
/* 19 */ 0x0114 ,
/* 1A */ 0x0115 ,
/* 1B */ 0x010F ,
/* 1C */ 0x010E ,
/* 1D */ 0x0110 ,
/* 1E */ 0x0111 ,
/* 1F */ 0x0112 ,
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/* 20 */ VX_INVALID ,
/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
/* 28 */ VX_INVALID ,
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/* 29 */ 0x027B ,
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/* 2A */ VX_INVALID ,
/* 2B */ VX_INVALID ,
/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
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} ,
{
/* 00 */ 0x00F0 ,
/* 01 */ 0x00F1 ,
/* 02 */ 0x00EE ,
/* 03 */ 0x00EF ,
/* 04 */ 0x00F4 ,
/* 05 */ 0x00F5 ,
/* 06 */ 0x00F2 ,
/* 07 */ 0x00F3 ,
/* 08 */ 0x0103 ,
/* 09 */ 0x0102 ,
/* 0A */ 0x0105 ,
/* 0B */ 0x0104 ,
/* 0C */ 0x00FF ,
/* 0D */ 0x00FE ,
/* 0E */ 0x0101 ,
/* 0F */ 0x0100 ,
/* 10 */ 0x00F8 ,
/* 11 */ 0x00F9 ,
/* 12 */ 0x00F6 ,
/* 13 */ 0x00F7 ,
/* 14 */ 0x00FC ,
/* 15 */ 0x00FD ,
/* 16 */ 0x00FA ,
/* 17 */ 0x00FB ,
/* 18 */ 0x010B ,
/* 19 */ 0x010A ,
/* 1A */ 0x010D ,
/* 1B */ 0x010C ,
/* 1C */ 0x0107 ,
/* 1D */ 0x0106 ,
/* 1E */ 0x0109 ,
/* 1F */ 0x0108 ,
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/* 20 */ 0x01E5 ,
/* 21 */ 0x01E4 ,
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/* 22 */ 0x00D5 ,
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/* 23 */ 0x01E6 ,
/* 24 */ 0x01E9 ,
/* 25 */ 0x01F4 ,
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/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
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/* 28 */ 0x0269 ,
/* 29 */ 0x026A ,
/* 2A */ 0x0265 ,
/* 2B */ 0x0264 ,
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/* 2C */ 0x0263 ,
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/* 2D */ 0x0268 ,
/* 2E */ 0x0267 ,
/* 2F */ 0x0266 ,
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/* 30 */ 0x0129 ,
/* 31 */ 0x0128 ,
/* 32 */ 0x012B ,
/* 33 */ 0x012A ,
/* 34 */ 0x012F ,
/* 35 */ 0x012E ,
/* 36 */ 0x012D ,
/* 37 */ 0x012C ,
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/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
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} ,
{
/* 00 */ 0x00B9 ,
/* 01 */ 0x00B8 ,
/* 02 */ 0x00C6 ,
/* 03 */ 0x00C9 ,
/* 04 */ 0x00C8 ,
/* 05 */ 0x00C7 ,
/* 06 */ 0x00BE ,
/* 07 */ 0x00BD ,
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/* 08 */ 0x01D1 ,
/* 09 */ 0x01D0 ,
/* 0A */ 0x01D5 ,
/* 0B */ 0x01D4 ,
/* 0C */ 0x01D3 ,
/* 0D */ 0x01CC ,
/* 0E */ 0x01CB ,
/* 0F */ 0x01CA ,
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/* 10 */ 0x0125 ,
/* 11 */ 0x0124 ,
/* 12 */ 0x0127 ,
/* 13 */ 0x0126 ,
/* 14 */ 0x0121 ,
/* 15 */ 0x0120 ,
/* 16 */ 0x0123 ,
/* 17 */ 0x0122 ,
/* 18 */ 0x0148 ,
/* 19 */ 0x0142 ,
/* 1A */ 0x0145 ,
/* 1B */ 0x0144 ,
/* 1C */ 0x0143 ,
/* 1D */ 0x0147 ,
/* 1E */ 0x0146 ,
/* 1F */ 0x0149 ,
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/* 20 */ 0x024F ,
/* 21 */ 0x0247 ,
/* 22 */ 0x0241 ,
/* 23 */ 0x0242 ,
/* 24 */ 0x0240 ,
/* 25 */ 0x024E ,
/* 26 */ 0x024D ,
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/* 27 */ 0x0244 ,
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/* 28 */ 0x0228 ,
/* 29 */ 0x0235 ,
/* 2A */ 0x0234 ,
/* 2B */ 0x0237 ,
/* 2C */ 0x0236 ,
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/* 2D */ 0x0233 ,
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/* 2E */ 0x0230 ,
/* 2F */ 0x022F ,
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/* 30 */ 0x017B ,
/* 31 */ 0x0178 ,
/* 32 */ 0x0179 ,
/* 33 */ 0x017C ,
/* 34 */ 0x017F ,
/* 35 */ 0x0180 ,
/* 36 */ 0x017D ,
/* 37 */ 0x017E ,
/* 38 */ 0x015E ,
/* 39 */ 0x015F ,
/* 3A */ 0x0160 ,
/* 3B */ 0x015B ,
/* 3C */ 0x015C ,
/* 3D */ 0x015D ,
/* 3E */ 0x0164 ,
/* 3F */ 0x0165 ,
} ,
{
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/* 00 */ 0x018F ,
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/* 01 */ 0x018E ,
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/* 02 */ 0x0191 ,
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/* 03 */ 0x0190 ,
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/* 04 */ 0x018B ,
/* 05 */ 0x018A ,
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/* 06 */ 0x018D ,
/* 07 */ 0x018C ,
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/* 08 */ 0x028A ,
/* 09 */ 0x0289 ,
/* 0A */ 0x028C ,
/* 0B */ 0x028B ,
/* 0C */ 0x0286 ,
/* 0D */ 0x0285 ,
/* 0E */ 0x0288 ,
/* 0F */ 0x0287 ,
/* 10 */ 0x0200 ,
/* 11 */ 0x0202 ,
/* 12 */ 0x0201 ,
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/* 13 */ 0x01FA ,
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/* 14 */ 0x01F9 ,
/* 15 */ 0x01FB ,
/* 16 */ 0x01FD ,
/* 17 */ 0x01FC ,
/* 18 */ 0x020D ,
/* 19 */ 0x020C ,
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/* 1A */ 0x0208 ,
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/* 1B */ 0x0204 ,
/* 1C */ 0x0203 ,
/* 1D */ 0x0205 ,
/* 1E */ 0x0207 ,
/* 1F */ 0x0206 ,
/* 20 */ 0x025D ,
/* 21 */ 0x025C ,
/* 22 */ 0x025B ,
/* 23 */ 0x025E ,
/* 24 */ 0x0261 ,
/* 25 */ 0x0262 ,
/* 26 */ 0x025F ,
/* 27 */ 0x0260 ,
/* 28 */ 0x0278 ,
/* 29 */ 0x0277 ,
/* 2A */ 0x027A ,
/* 2B */ 0x0279 ,
/* 2C */ 0x0274 ,
/* 2D */ 0x0273 ,
/* 2E */ 0x0276 ,
/* 2F */ 0x0275 ,
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/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
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} ,
{
/* 00 */ 0x00CC ,
/* 01 */ 0x00CD ,
/* 02 */ 0x00CA ,
/* 03 */ 0x00CB ,
/* 04 */ 0x00D0 ,
/* 05 */ 0x00D1 ,
/* 06 */ 0x00CE ,
/* 07 */ 0x00CF ,
/* 08 */ 0x01E1 ,
/* 09 */ 0x01E0 ,
/* 0A */ 0x01E3 ,
/* 0B */ 0x01E2 ,
/* 0C */ 0x01DD ,
/* 0D */ 0x01DC ,
/* 0E */ 0x01DF ,
/* 0F */ 0x01DE ,
/* 10 */ 0x014F ,
/* 11 */ 0x014E ,
/* 12 */ 0x0151 ,
/* 13 */ 0x0150 ,
/* 14 */ 0x014B ,
/* 15 */ 0x014A ,
/* 16 */ 0x014D ,
/* 17 */ 0x014C ,
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/* 18 */ VX_INVALID ,
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/* 19 */ 0x0152 ,
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/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
/* 1C */ VX_INVALID ,
/* 1D */ VX_INVALID ,
/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
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/* 20 */ 0x0258 ,
/* 21 */ 0x0259 ,
/* 22 */ 0x0256 ,
/* 23 */ 0x0257 ,
/* 24 */ 0x0253 ,
/* 25 */ 0x0252 ,
/* 26 */ 0x0255 ,
/* 27 */ 0x0254 ,
/* 28 */ 0x023B ,
/* 29 */ 0x023D ,
/* 2A */ 0x023C ,
/* 2B */ 0x0239 ,
/* 2C */ 0x0238 ,
/* 2D */ 0x023A ,
/* 2E */ 0x023E ,
/* 2F */ 0x023F ,
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/* 30 */ 0x0186 ,
/* 31 */ 0x0185 ,
/* 32 */ 0x0188 ,
/* 33 */ 0x0187 ,
/* 34 */ 0x0182 ,
/* 35 */ 0x0181 ,
/* 36 */ 0x0184 ,
/* 37 */ 0x0183 ,
/* 38 */ 0x016C ,
/* 39 */ 0x016B ,
/* 3A */ 0x016E ,
/* 3B */ 0x016D ,
/* 3C */ 0x0168 ,
/* 3D */ 0x0167 ,
/* 3E */ 0x016A ,
/* 3F */ 0x0169 ,
} ,
{
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/* 00 */ 0x0199 ,
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/* 01 */ 0x0196 ,
/* 02 */ 0x0197 ,
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/* 03 */ 0x0198 ,
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/* 04 */ 0x0193 ,
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/* 05 */ 0x0192 ,
/* 06 */ 0x0195 ,
/* 07 */ 0x0194 ,
/* 08 */ 0x028F ,
/* 09 */ 0x0290 ,
/* 0A */ 0x028D ,
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/* 0B */ 0x028E ,
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/* 0C */ 0x0293 ,
/* 0D */ 0x0294 ,
/* 0E */ 0x0291 ,
/* 0F */ 0x0292 ,
/* 10 */ 0x021B ,
/* 11 */ 0x021A ,
/* 12 */ 0x021D ,
/* 13 */ 0x021C ,
/* 14 */ 0x0217 ,
/* 15 */ 0x0216 ,
/* 16 */ 0x0219 ,
/* 17 */ 0x0218 ,
/* 18 */ 0x0220 ,
/* 19 */ 0x0221 ,
/* 1A */ 0x021E ,
/* 1B */ 0x021F ,
/* 1C */ 0x0224 ,
/* 1D */ 0x0225 ,
/* 1E */ 0x0222 ,
/* 1F */ 0x0223 ,
/* 20 */ 0x01EC ,
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/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
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/* 28 */ 0x0271 ,
/* 29 */ 0x0272 ,
/* 2A */ 0x026D ,
/* 2B */ 0x026C ,
/* 2C */ 0x026B ,
/* 2D */ 0x0270 ,
/* 2E */ 0x026F ,
/* 2F */ 0x026E ,
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/* 30 */ 0x0136 ,
/* 31 */ 0x0137 ,
/* 32 */ 0x0133 ,
/* 33 */ 0x0134 ,
/* 34 */ 0x0135 ,
/* 35 */ 0x0130 ,
/* 36 */ 0x0131 ,
/* 37 */ 0x0132 ,
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/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeAddressSize [ ] [ 3 ] =
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{
{
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/* 00 */ 0x02CD ,
/* 01 */ 0x02D0 ,
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/* 02 */ 0x02EC ,
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} ,
} ;
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const VXOpcodeTreeNode optreeOperandSize [ ] [ 3 ] =
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{
{
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/* 00 */ 0x03E0 ,
/* 01 */ 0x03E1 ,
/* 02 */ 0x03E2 ,
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} ,
{
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/* 00 */ 0x0409 ,
/* 01 */ 0x040A ,
/* 02 */ 0x040B ,
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} ,
{
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/* 00 */ 0x033D ,
/* 01 */ 0x0343 ,
/* 02 */ 0x035E ,
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} ,
{
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/* 00 */ 0x0341 ,
/* 01 */ 0x0342 ,
/* 02 */ 0x0364 ,
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} ,
{
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/* 00 */ 0x0344 ,
/* 01 */ 0x033E ,
/* 02 */ 0x0365 ,
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} ,
{
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/* 00 */ 0x0340 ,
/* 01 */ 0x033F ,
/* 02 */ 0x0360 ,
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} ,
{
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/* 00 */ 0x007F ,
/* 01 */ 0x0080 ,
/* 02 */ 0x007E ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x000F ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0010 ) ,
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/* 02 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0011 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0012 ) ,
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/* 02 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02B8 ,
/* 01 */ 0x02B6 ,
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/* 02 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x03A1 ,
/* 01 */ 0x03A0 ,
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/* 02 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x0050 ,
/* 01 */ 0x009E ,
/* 02 */ 0x0052 ,
} ,
{
/* 00 */ 0x009D ,
/* 01 */ 0x0051 ,
/* 02 */ 0x0084 ,
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x001E ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x001F ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0020 ) ,
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0021 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0022 ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0023 ) ,
} ,
{
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/* 00 */ 0x0372 ,
/* 01 */ 0x0369 ,
/* 02 */ 0x036F ,
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} ,
{
/* 00 */ 0x007B ,
/* 01 */ 0x0078 ,
/* 02 */ 0x0079 ,
} ,
{
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/* 00 */ 0x0540 ,
/* 01 */ 0x053E ,
/* 02 */ 0x053F ,
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} ,
{
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/* 00 */ 0x0303 ,
/* 01 */ 0x0301 ,
/* 02 */ 0x0302 ,
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} ,
{
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/* 00 */ 0x0504 ,
/* 01 */ 0x0502 ,
/* 02 */ 0x0503 ,
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} ,
{
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/* 00 */ 0x05BB ,
/* 01 */ 0x05BA ,
/* 02 */ 0x05D5 ,
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} ,
{
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/* 00 */ 0x05B9 ,
/* 01 */ 0x05BC ,
/* 02 */ 0x05D6 ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x000E ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x000F ) ,
/* 02 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0010 ) ,
} ,
{
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/* 00 */ 0x02C6 ,
/* 01 */ 0x02C4 ,
/* 02 */ 0x02C5 ,
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} ,
} ;
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const VXOpcodeTreeNode optreeMode [ ] [ 2 ] =
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{
{
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/* 00 */ 0x04AA ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0445 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04AD ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0553 ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x000D ) ,
} ,
{
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/* 00 */ 0x0555 ,
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/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x000E ) ,
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x000F ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0010 ) ,
} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0011 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VENDOR , 0x0012 ) ,
} ,
{
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/* 00 */ 0x04AC ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0446 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04A9 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0443 ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x009F ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x00A0 ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x0001 ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x0004 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04BA ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04BB ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x044B ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x044C ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0038 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0033 ,
/* 01 */ 0x0375 ,
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} ,
{
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/* 00 */ 0x0011 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0398 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0007 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04FC ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x002A ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0546 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x06B3 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0073 ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x004F ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04C0 ,
/* 01 */ 0x04BF ,
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} ,
{
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/* 00 */ 0x04BC ,
/* 01 */ 0x04BE ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x04BD ,
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} ,
{
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/* 00 */ 0x0451 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x044E ,
/* 01 */ 0x0450 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x044F ,
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} ,
{
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/* 00 */ 0x02F6 ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0014 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VEXW , 0x0015 ) ,
} ,
{
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/* 00 */ 0x02F3 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02BC ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x0003 ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x0002 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04F0 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02DC ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x004D ,
/* 01 */ 0x004B ,
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} ,
} ;
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const VXOpcodeTreeNode optreeVendor [ ] [ 2 ] =
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{
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05AC ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05B2 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05EB ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05F3 ,
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} ,
{
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/* 00 */ 0x05EC ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05B4 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05B3 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05ED ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x053A ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ 0x0056 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0530 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x02C1 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x04D5 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x0552 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x0554 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x02BE ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x02BF ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x02C3 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x02C2 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05EA ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05F2 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05E8 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05E9 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05F4 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05AD ,
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} ,
} ;
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const VXOpcodeTreeNode optree3dnow [ ] [ 256 ] =
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{
{
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/* 00 */ VX_INVALID ,
/* 01 */ VX_INVALID ,
/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
/* 05 */ VX_INVALID ,
/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
/* 08 */ VX_INVALID ,
/* 09 */ VX_INVALID ,
/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
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/* 0C */ 0x0407 ,
/* 0D */ 0x0406 ,
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/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
/* 10 */ VX_INVALID ,
/* 11 */ VX_INVALID ,
/* 12 */ VX_INVALID ,
/* 13 */ VX_INVALID ,
/* 14 */ VX_INVALID ,
/* 15 */ VX_INVALID ,
/* 16 */ VX_INVALID ,
/* 17 */ VX_INVALID ,
/* 18 */ VX_INVALID ,
/* 19 */ VX_INVALID ,
/* 1A */ VX_INVALID ,
/* 1B */ VX_INVALID ,
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/* 1C */ 0x03E7 ,
/* 1D */ 0x03E6 ,
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/* 1E */ VX_INVALID ,
/* 1F */ VX_INVALID ,
/* 20 */ VX_INVALID ,
/* 21 */ VX_INVALID ,
/* 22 */ VX_INVALID ,
/* 23 */ VX_INVALID ,
/* 24 */ VX_INVALID ,
/* 25 */ VX_INVALID ,
/* 26 */ VX_INVALID ,
/* 27 */ VX_INVALID ,
/* 28 */ VX_INVALID ,
/* 29 */ VX_INVALID ,
/* 2A */ VX_INVALID ,
/* 2B */ VX_INVALID ,
/* 2C */ VX_INVALID ,
/* 2D */ VX_INVALID ,
/* 2E */ VX_INVALID ,
/* 2F */ VX_INVALID ,
/* 30 */ VX_INVALID ,
/* 31 */ VX_INVALID ,
/* 32 */ VX_INVALID ,
/* 33 */ VX_INVALID ,
/* 34 */ VX_INVALID ,
/* 35 */ VX_INVALID ,
/* 36 */ VX_INVALID ,
/* 37 */ VX_INVALID ,
/* 38 */ VX_INVALID ,
/* 39 */ VX_INVALID ,
/* 3A */ VX_INVALID ,
/* 3B */ VX_INVALID ,
/* 3C */ VX_INVALID ,
/* 3D */ VX_INVALID ,
/* 3E */ VX_INVALID ,
/* 3F */ VX_INVALID ,
/* 40 */ VX_INVALID ,
/* 41 */ VX_INVALID ,
/* 42 */ VX_INVALID ,
/* 43 */ VX_INVALID ,
/* 44 */ VX_INVALID ,
/* 45 */ VX_INVALID ,
/* 46 */ VX_INVALID ,
/* 47 */ VX_INVALID ,
/* 48 */ VX_INVALID ,
/* 49 */ VX_INVALID ,
/* 4A */ VX_INVALID ,
/* 4B */ VX_INVALID ,
/* 4C */ VX_INVALID ,
/* 4D */ VX_INVALID ,
/* 4E */ VX_INVALID ,
/* 4F */ VX_INVALID ,
/* 50 */ VX_INVALID ,
/* 51 */ VX_INVALID ,
/* 52 */ VX_INVALID ,
/* 53 */ VX_INVALID ,
/* 54 */ VX_INVALID ,
/* 55 */ VX_INVALID ,
/* 56 */ VX_INVALID ,
/* 57 */ VX_INVALID ,
/* 58 */ VX_INVALID ,
/* 59 */ VX_INVALID ,
/* 5A */ VX_INVALID ,
/* 5B */ VX_INVALID ,
/* 5C */ VX_INVALID ,
/* 5D */ VX_INVALID ,
/* 5E */ VX_INVALID ,
/* 5F */ VX_INVALID ,
/* 60 */ VX_INVALID ,
/* 61 */ VX_INVALID ,
/* 62 */ VX_INVALID ,
/* 63 */ VX_INVALID ,
/* 64 */ VX_INVALID ,
/* 65 */ VX_INVALID ,
/* 66 */ VX_INVALID ,
/* 67 */ VX_INVALID ,
/* 68 */ VX_INVALID ,
/* 69 */ VX_INVALID ,
/* 6A */ VX_INVALID ,
/* 6B */ VX_INVALID ,
/* 6C */ VX_INVALID ,
/* 6D */ VX_INVALID ,
/* 6E */ VX_INVALID ,
/* 6F */ VX_INVALID ,
/* 70 */ VX_INVALID ,
/* 71 */ VX_INVALID ,
/* 72 */ VX_INVALID ,
/* 73 */ VX_INVALID ,
/* 74 */ VX_INVALID ,
/* 75 */ VX_INVALID ,
/* 76 */ VX_INVALID ,
/* 77 */ VX_INVALID ,
/* 78 */ VX_INVALID ,
/* 79 */ VX_INVALID ,
/* 7A */ VX_INVALID ,
/* 7B */ VX_INVALID ,
/* 7C */ VX_INVALID ,
/* 7D */ VX_INVALID ,
/* 7E */ VX_INVALID ,
/* 7F */ VX_INVALID ,
/* 80 */ VX_INVALID ,
/* 81 */ VX_INVALID ,
/* 82 */ VX_INVALID ,
/* 83 */ VX_INVALID ,
/* 84 */ VX_INVALID ,
/* 85 */ VX_INVALID ,
/* 86 */ VX_INVALID ,
/* 87 */ VX_INVALID ,
/* 88 */ VX_INVALID ,
/* 89 */ VX_INVALID ,
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/* 8A */ 0x03F0 ,
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/* 8B */ VX_INVALID ,
/* 8C */ VX_INVALID ,
/* 8D */ VX_INVALID ,
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/* 8E */ 0x03F1 ,
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/* 8F */ VX_INVALID ,
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/* 90 */ 0x03EB ,
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/* 91 */ VX_INVALID ,
/* 92 */ VX_INVALID ,
/* 93 */ VX_INVALID ,
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/* 94 */ 0x03EE ,
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/* 95 */ VX_INVALID ,
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/* 96 */ 0x03F2 ,
/* 97 */ 0x03F6 ,
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/* 98 */ VX_INVALID ,
/* 99 */ VX_INVALID ,
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/* 9A */ 0x03F7 ,
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/* 9B */ VX_INVALID ,
/* 9C */ VX_INVALID ,
/* 9D */ VX_INVALID ,
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/* 9E */ 0x03E9 ,
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/* 9F */ VX_INVALID ,
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/* A0 */ 0x03EC ,
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/* A1 */ VX_INVALID ,
/* A2 */ VX_INVALID ,
/* A3 */ VX_INVALID ,
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/* A4 */ 0x03ED ,
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/* A5 */ VX_INVALID ,
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/* A6 */ 0x03F3 ,
/* A7 */ 0x03F5 ,
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/* A8 */ VX_INVALID ,
/* A9 */ VX_INVALID ,
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/* AA */ 0x03F8 ,
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/* AB */ VX_INVALID ,
/* AC */ VX_INVALID ,
/* AD */ VX_INVALID ,
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/* AE */ 0x03E8 ,
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/* AF */ VX_INVALID ,
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/* B0 */ 0x03EA ,
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/* B1 */ VX_INVALID ,
/* B2 */ VX_INVALID ,
/* B3 */ VX_INVALID ,
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/* B4 */ 0x03EF ,
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/* B5 */ VX_INVALID ,
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/* B6 */ 0x03F4 ,
/* B7 */ 0x0433 ,
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/* B8 */ VX_INVALID ,
/* B9 */ VX_INVALID ,
/* BA */ VX_INVALID ,
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/* BB */ 0x0499 ,
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/* BC */ VX_INVALID ,
/* BD */ VX_INVALID ,
/* BE */ VX_INVALID ,
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/* BF */ 0x03C7 ,
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/* C0 */ VX_INVALID ,
/* C1 */ VX_INVALID ,
/* C2 */ VX_INVALID ,
/* C3 */ VX_INVALID ,
/* C4 */ VX_INVALID ,
/* C5 */ VX_INVALID ,
/* C6 */ VX_INVALID ,
/* C7 */ VX_INVALID ,
/* C8 */ VX_INVALID ,
/* C9 */ VX_INVALID ,
/* CA */ VX_INVALID ,
/* CB */ VX_INVALID ,
/* CC */ VX_INVALID ,
/* CD */ VX_INVALID ,
/* CE */ VX_INVALID ,
/* CF */ VX_INVALID ,
/* D0 */ VX_INVALID ,
/* D1 */ VX_INVALID ,
/* D2 */ VX_INVALID ,
/* D3 */ VX_INVALID ,
/* D4 */ VX_INVALID ,
/* D5 */ VX_INVALID ,
/* D6 */ VX_INVALID ,
/* D7 */ VX_INVALID ,
/* D8 */ VX_INVALID ,
/* D9 */ VX_INVALID ,
/* DA */ VX_INVALID ,
/* DB */ VX_INVALID ,
/* DC */ VX_INVALID ,
/* DD */ VX_INVALID ,
/* DE */ VX_INVALID ,
/* DF */ VX_INVALID ,
/* E0 */ VX_INVALID ,
/* E1 */ VX_INVALID ,
/* E2 */ VX_INVALID ,
/* E3 */ VX_INVALID ,
/* E4 */ VX_INVALID ,
/* E5 */ VX_INVALID ,
/* E6 */ VX_INVALID ,
/* E7 */ VX_INVALID ,
/* E8 */ VX_INVALID ,
/* E9 */ VX_INVALID ,
/* EA */ VX_INVALID ,
/* EB */ VX_INVALID ,
/* EC */ VX_INVALID ,
/* ED */ VX_INVALID ,
/* EE */ VX_INVALID ,
/* EF */ VX_INVALID ,
/* F0 */ VX_INVALID ,
/* F1 */ VX_INVALID ,
/* F2 */ VX_INVALID ,
/* F3 */ VX_INVALID ,
/* F4 */ VX_INVALID ,
/* F5 */ VX_INVALID ,
/* F6 */ VX_INVALID ,
/* F7 */ VX_INVALID ,
/* F8 */ VX_INVALID ,
/* F9 */ VX_INVALID ,
/* FA */ VX_INVALID ,
/* FB */ VX_INVALID ,
/* FC */ VX_INVALID ,
/* FD */ VX_INVALID ,
/* FE */ VX_INVALID ,
/* FF */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeVex [ ] [ 16 ] =
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{
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0024 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0004 ) ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
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/* 05 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0005 ) ,
/* 06 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0006 ) ,
/* 07 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0007 ) ,
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/* 08 */ VX_INVALID ,
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/* 09 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0008 ) ,
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/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
/* 0C */ VX_INVALID ,
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/* 0D */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0009 ) ,
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/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : MODE , 0x0026 ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0004 ) ,
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/* 02 */ VX_INVALID ,
/* 03 */ VX_INVALID ,
/* 04 */ VX_INVALID ,
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/* 05 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0005 ) ,
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/* 06 */ VX_INVALID ,
/* 07 */ VX_INVALID ,
/* 08 */ VX_INVALID ,
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/* 09 */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0008 ) ,
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/* 0A */ VX_INVALID ,
/* 0B */ VX_INVALID ,
/* 0C */ VX_INVALID ,
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/* 0D */ NODE ( VXOpcodeTreeNodeType : : TABLE , 0x0009 ) ,
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/* 0E */ VX_INVALID ,
/* 0F */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeVexW [ ] [ 2 ] =
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{
{
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/* 00 */ 0x061D ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x061C ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0692 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0691 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x057B ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0008 ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05A6 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05A5 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05A7 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x05A4 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x061E ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x061B ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x0009 ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x061F ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0620 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0621 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x0622 ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x000A ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x000B ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x000C ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x000D ) ,
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/* 01 */ VX_INVALID ,
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} ,
{
/* 00 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x000E ) ,
/* 01 */ NODE ( VXOpcodeTreeNodeType : : VEXL , 0x000F ) ,
} ,
{
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/* 00 */ 0x0579 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x0578 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x060B ,
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/* 01 */ VX_INVALID ,
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} ,
} ;
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const VXOpcodeTreeNode optreeVexL [ ] [ 2 ] =
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{
{
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/* 00 */ 0x069C ,
/* 01 */ 0x069B ,
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} ,
{
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/* 00 */ 0x0660 ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x065A ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x065E ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x063F ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x065F ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x065B ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x065D ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x057A ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x061A ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x05A0 ,
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} ,
{
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/* 00 */ VX_INVALID ,
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/* 01 */ 0x059A ,
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} ,
{
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/* 00 */ 0x062C ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x062E ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x062D ,
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/* 01 */ VX_INVALID ,
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} ,
{
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/* 00 */ 0x062F ,
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/* 01 */ VX_INVALID ,
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} ,
} ;
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# undef VX_INVALID
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# undef NODE
# define OPI_NONE { VXDefinedOperandType::NONE, VXDefinedOperandSize::NA }
# define OPI_AL { VXDefinedOperandType::AL, VXDefinedOperandSize::B }
# define OPI_AX { VXDefinedOperandType::AX, VXDefinedOperandSize::W }
# define OPI_Av { VXDefinedOperandType::A, VXDefinedOperandSize::V }
# define OPI_C { VXDefinedOperandType::C, VXDefinedOperandSize::NA }
# define OPI_CL { VXDefinedOperandType::CL, VXDefinedOperandSize::B }
# define OPI_CS { VXDefinedOperandType::CS, VXDefinedOperandSize::NA }
# define OPI_CX { VXDefinedOperandType::CX, VXDefinedOperandSize::W }
# define OPI_D { VXDefinedOperandType::D, VXDefinedOperandSize::NA }
# define OPI_DL { VXDefinedOperandType::DL, VXDefinedOperandSize::B }
# define OPI_DS { VXDefinedOperandType::DS, VXDefinedOperandSize::NA }
# define OPI_DX { VXDefinedOperandType::DX, VXDefinedOperandSize::W }
# define OPI_E { VXDefinedOperandType::E, VXDefinedOperandSize::NA }
# define OPI_ES { VXDefinedOperandType::ES, VXDefinedOperandSize::NA }
# define OPI_Eb { VXDefinedOperandType::E, VXDefinedOperandSize::B }
# define OPI_Ed { VXDefinedOperandType::E, VXDefinedOperandSize::D }
# define OPI_Eq { VXDefinedOperandType::E, VXDefinedOperandSize::Q }
# define OPI_Ev { VXDefinedOperandType::E, VXDefinedOperandSize::V }
# define OPI_Ew { VXDefinedOperandType::E, VXDefinedOperandSize::W }
# define OPI_Ey { VXDefinedOperandType::E, VXDefinedOperandSize::Y }
# define OPI_Ez { VXDefinedOperandType::E, VXDefinedOperandSize::Z }
# define OPI_FS { VXDefinedOperandType::FS, VXDefinedOperandSize::NA }
# define OPI_Fv { VXDefinedOperandType::F, VXDefinedOperandSize::V }
# define OPI_G { VXDefinedOperandType::G, VXDefinedOperandSize::NA }
# define OPI_GS { VXDefinedOperandType::GS, VXDefinedOperandSize::NA }
# define OPI_Gb { VXDefinedOperandType::G, VXDefinedOperandSize::B }
# define OPI_Gd { VXDefinedOperandType::G, VXDefinedOperandSize::D }
# define OPI_Gq { VXDefinedOperandType::G, VXDefinedOperandSize::Q }
# define OPI_Gv { VXDefinedOperandType::G, VXDefinedOperandSize::V }
# define OPI_Gw { VXDefinedOperandType::G, VXDefinedOperandSize::W }
# define OPI_Gy { VXDefinedOperandType::G, VXDefinedOperandSize::Y }
# define OPI_Gz { VXDefinedOperandType::G, VXDefinedOperandSize::Z }
# define OPI_H { VXDefinedOperandType::H, VXDefinedOperandSize::X }
# define OPI_Hqq { VXDefinedOperandType::H, VXDefinedOperandSize::QQ }
# define OPI_Hx { VXDefinedOperandType::H, VXDefinedOperandSize::X }
# define OPI_I1 { VXDefinedOperandType::I1, VXDefinedOperandSize::NA }
# define OPI_Ib { VXDefinedOperandType::I, VXDefinedOperandSize::B }
# define OPI_Iv { VXDefinedOperandType::I, VXDefinedOperandSize::V }
# define OPI_Iw { VXDefinedOperandType::I, VXDefinedOperandSize::W }
# define OPI_Iz { VXDefinedOperandType::I, VXDefinedOperandSize::Z }
# define OPI_Jb { VXDefinedOperandType::J, VXDefinedOperandSize::B }
# define OPI_Jv { VXDefinedOperandType::J, VXDefinedOperandSize::V }
# define OPI_Jz { VXDefinedOperandType::J, VXDefinedOperandSize::Z }
# define OPI_L { VXDefinedOperandType::L, VXDefinedOperandSize::O }
# define OPI_Lx { VXDefinedOperandType::L, VXDefinedOperandSize::X }
# define OPI_M { VXDefinedOperandType::M, VXDefinedOperandSize::NA }
# define OPI_Mb { VXDefinedOperandType::M, VXDefinedOperandSize::B }
# define OPI_MbRd { VXDefinedOperandType::MR, VXDefinedOperandSize::BD }
# define OPI_MbRv { VXDefinedOperandType::MR, VXDefinedOperandSize::BV }
# define OPI_Md { VXDefinedOperandType::M, VXDefinedOperandSize::D }
# define OPI_MdRy { VXDefinedOperandType::MR, VXDefinedOperandSize::DY }
# define OPI_MdU { VXDefinedOperandType::MU, VXDefinedOperandSize::DO }
# define OPI_Mdq { VXDefinedOperandType::M, VXDefinedOperandSize::DQ }
# define OPI_Mo { VXDefinedOperandType::M, VXDefinedOperandSize::O }
# define OPI_Mq { VXDefinedOperandType::M, VXDefinedOperandSize::Q }
# define OPI_MqU { VXDefinedOperandType::MU, VXDefinedOperandSize::QO }
# define OPI_Ms { VXDefinedOperandType::M, VXDefinedOperandSize::W }
# define OPI_Mt { VXDefinedOperandType::M, VXDefinedOperandSize::T }
# define OPI_Mv { VXDefinedOperandType::M, VXDefinedOperandSize::V }
# define OPI_Mw { VXDefinedOperandType::M, VXDefinedOperandSize::W }
# define OPI_MwRd { VXDefinedOperandType::MR, VXDefinedOperandSize::WD }
# define OPI_MwRv { VXDefinedOperandType::MR, VXDefinedOperandSize::WV }
# define OPI_MwRy { VXDefinedOperandType::MR, VXDefinedOperandSize::WY }
# define OPI_MwU { VXDefinedOperandType::MU, VXDefinedOperandSize::WO }
# define OPI_N { VXDefinedOperandType::N, VXDefinedOperandSize::Q }
# define OPI_Ob { VXDefinedOperandType::O, VXDefinedOperandSize::B }
# define OPI_Ov { VXDefinedOperandType::O, VXDefinedOperandSize::V }
# define OPI_Ow { VXDefinedOperandType::O, VXDefinedOperandSize::W }
# define OPI_P { VXDefinedOperandType::P, VXDefinedOperandSize::Q }
# define OPI_Q { VXDefinedOperandType::Q, VXDefinedOperandSize::Q }
# define OPI_R { VXDefinedOperandType::R, VXDefinedOperandSize::RDQ }
# define OPI_R0b { VXDefinedOperandType::R0, VXDefinedOperandSize::B }
# define OPI_R0v { VXDefinedOperandType::R0, VXDefinedOperandSize::V }
# define OPI_R0w { VXDefinedOperandType::R0, VXDefinedOperandSize::W }
# define OPI_R0y { VXDefinedOperandType::R0, VXDefinedOperandSize::Y }
# define OPI_R0z { VXDefinedOperandType::R0, VXDefinedOperandSize::Z }
# define OPI_R1b { VXDefinedOperandType::R1, VXDefinedOperandSize::B }
# define OPI_R1v { VXDefinedOperandType::R1, VXDefinedOperandSize::V }
# define OPI_R1w { VXDefinedOperandType::R1, VXDefinedOperandSize::W }
# define OPI_R1y { VXDefinedOperandType::R1, VXDefinedOperandSize::Y }
# define OPI_R1z { VXDefinedOperandType::R1, VXDefinedOperandSize::Z }
# define OPI_R2b { VXDefinedOperandType::R2, VXDefinedOperandSize::B }
# define OPI_R2v { VXDefinedOperandType::R2, VXDefinedOperandSize::V }
# define OPI_R2w { VXDefinedOperandType::R2, VXDefinedOperandSize::W }
# define OPI_R2y { VXDefinedOperandType::R2, VXDefinedOperandSize::Y }
# define OPI_R2z { VXDefinedOperandType::R2, VXDefinedOperandSize::Z }
# define OPI_R3b { VXDefinedOperandType::R3, VXDefinedOperandSize::B }
# define OPI_R3v { VXDefinedOperandType::R3, VXDefinedOperandSize::V }
# define OPI_R3w { VXDefinedOperandType::R3, VXDefinedOperandSize::W }
# define OPI_R3y { VXDefinedOperandType::R3, VXDefinedOperandSize::Y }
# define OPI_R3z { VXDefinedOperandType::R3, VXDefinedOperandSize::Z }
# define OPI_R4b { VXDefinedOperandType::R4, VXDefinedOperandSize::B }
# define OPI_R4v { VXDefinedOperandType::R4, VXDefinedOperandSize::V }
# define OPI_R4w { VXDefinedOperandType::R4, VXDefinedOperandSize::W }
# define OPI_R4y { VXDefinedOperandType::R4, VXDefinedOperandSize::Y }
# define OPI_R4z { VXDefinedOperandType::R4, VXDefinedOperandSize::Z }
# define OPI_R5b { VXDefinedOperandType::R5, VXDefinedOperandSize::B }
# define OPI_R5v { VXDefinedOperandType::R5, VXDefinedOperandSize::V }
# define OPI_R5w { VXDefinedOperandType::R5, VXDefinedOperandSize::W }
# define OPI_R5y { VXDefinedOperandType::R5, VXDefinedOperandSize::Y }
# define OPI_R5z { VXDefinedOperandType::R5, VXDefinedOperandSize::Z }
# define OPI_R6b { VXDefinedOperandType::R6, VXDefinedOperandSize::B }
# define OPI_R6v { VXDefinedOperandType::R6, VXDefinedOperandSize::V }
# define OPI_R6w { VXDefinedOperandType::R6, VXDefinedOperandSize::W }
# define OPI_R6y { VXDefinedOperandType::R6, VXDefinedOperandSize::Y }
# define OPI_R6z { VXDefinedOperandType::R6, VXDefinedOperandSize::Z }
# define OPI_R7b { VXDefinedOperandType::R7, VXDefinedOperandSize::B }
# define OPI_R7v { VXDefinedOperandType::R7, VXDefinedOperandSize::V }
# define OPI_R7w { VXDefinedOperandType::R7, VXDefinedOperandSize::W }
# define OPI_R7y { VXDefinedOperandType::R7, VXDefinedOperandSize::Y }
# define OPI_R7z { VXDefinedOperandType::R7, VXDefinedOperandSize::Z }
# define OPI_S { VXDefinedOperandType::S, VXDefinedOperandSize::W }
# define OPI_SS { VXDefinedOperandType::SS, VXDefinedOperandSize::NA }
# define OPI_ST0 { VXDefinedOperandType::ST0, VXDefinedOperandSize::NA }
# define OPI_ST1 { VXDefinedOperandType::ST1, VXDefinedOperandSize::NA }
# define OPI_ST2 { VXDefinedOperandType::ST2, VXDefinedOperandSize::NA }
# define OPI_ST3 { VXDefinedOperandType::ST3, VXDefinedOperandSize::NA }
# define OPI_ST4 { VXDefinedOperandType::ST4, VXDefinedOperandSize::NA }
# define OPI_ST5 { VXDefinedOperandType::ST5, VXDefinedOperandSize::NA }
# define OPI_ST6 { VXDefinedOperandType::ST6, VXDefinedOperandSize::NA }
# define OPI_ST7 { VXDefinedOperandType::ST7, VXDefinedOperandSize::NA }
# define OPI_U { VXDefinedOperandType::U, VXDefinedOperandSize::O }
# define OPI_Ux { VXDefinedOperandType::U, VXDefinedOperandSize::X }
# define OPI_V { VXDefinedOperandType::V, VXDefinedOperandSize::DQ }
# define OPI_Vdq { VXDefinedOperandType::V, VXDefinedOperandSize::DQ }
# define OPI_Vqq { VXDefinedOperandType::V, VXDefinedOperandSize::QQ }
# define OPI_Vsd { VXDefinedOperandType::V, VXDefinedOperandSize::Q }
# define OPI_Vx { VXDefinedOperandType::V, VXDefinedOperandSize::X }
# define OPI_W { VXDefinedOperandType::W, VXDefinedOperandSize::DQ }
# define OPI_Wdq { VXDefinedOperandType::W, VXDefinedOperandSize::DQ }
# define OPI_Wqq { VXDefinedOperandType::W, VXDefinedOperandSize::QQ }
# define OPI_Wsd { VXDefinedOperandType::W, VXDefinedOperandSize::Q }
# define OPI_Wx { VXDefinedOperandType::W, VXDefinedOperandSize::X }
# define OPI_eAX { VXDefinedOperandType::EAX, VXDefinedOperandSize::Z }
# define OPI_eCX { VXDefinedOperandType::ECX, VXDefinedOperandSize::Z }
# define OPI_eDX { VXDefinedOperandType::EDX, VXDefinedOperandSize::Z }
# define OPI_rAX { VXDefinedOperandType::RAX, VXDefinedOperandSize::V }
# define OPI_rCX { VXDefinedOperandType::RCX, VXDefinedOperandSize::V }
# define OPI_rDX { VXDefinedOperandType::RDX, VXDefinedOperandSize::V }
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# define OPI_sIb { VXDefinedOperandType::sI, VXDefinedOperandSize::B }
# define OPI_sIz { VXDefinedOperandType::sI, VXDefinedOperandSize::Z }
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const VXInstructionDefinition instrDefinitions [ ] =
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{
/* 000 */ { VXInstructionMnemonic : : INVALID , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 001 */ { VXInstructionMnemonic : : AAA , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 002 */ { VXInstructionMnemonic : : AAD , { OPI_Ib , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 003 */ { VXInstructionMnemonic : : AAM , { OPI_Ib , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 004 */ { VXInstructionMnemonic : : AAS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 005 */ { VXInstructionMnemonic : : ADC , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 006 */ { VXInstructionMnemonic : : ADC , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_READWRITE } ,
/* 007 */ { VXInstructionMnemonic : : ADC , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 | IDF_OPERAND1_READWRITE } ,
/* 008 */ { VXInstructionMnemonic : : ADC , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 009 */ { VXInstructionMnemonic : : ADC , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 00A */ { VXInstructionMnemonic : : ADC , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 00B */ { VXInstructionMnemonic : : ADC , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 00C */ { VXInstructionMnemonic : : ADC , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 00D */ { VXInstructionMnemonic : : ADC , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 00E */ { VXInstructionMnemonic : : ADC , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 00F */ { VXInstructionMnemonic : : ADD , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 010 */ { VXInstructionMnemonic : : ADD , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_READWRITE } ,
/* 011 */ { VXInstructionMnemonic : : ADD , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 | IDF_OPERAND1_READWRITE } ,
/* 012 */ { VXInstructionMnemonic : : ADD , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 013 */ { VXInstructionMnemonic : : ADD , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 014 */ { VXInstructionMnemonic : : ADD , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 015 */ { VXInstructionMnemonic : : ADD , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 016 */ { VXInstructionMnemonic : : ADD , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 017 */ { VXInstructionMnemonic : : ADD , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 018 */ { VXInstructionMnemonic : : ADD , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 019 */ { VXInstructionMnemonic : : ADDPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 01A */ { VXInstructionMnemonic : : ADDPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 01B */ { VXInstructionMnemonic : : ADDSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 01C */ { VXInstructionMnemonic : : ADDSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 01D */ { VXInstructionMnemonic : : ADDSUBPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 01E */ { VXInstructionMnemonic : : ADDSUBPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 01F */ { VXInstructionMnemonic : : AESDEC , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 020 */ { VXInstructionMnemonic : : AESDECLAST , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 021 */ { VXInstructionMnemonic : : AESENC , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 022 */ { VXInstructionMnemonic : : AESENCLAST , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 023 */ { VXInstructionMnemonic : : AESIMC , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 024 */ { VXInstructionMnemonic : : AESKEYGENASSIST , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 025 */ { VXInstructionMnemonic : : AND , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 026 */ { VXInstructionMnemonic : : AND , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 027 */ { VXInstructionMnemonic : : AND , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 028 */ { VXInstructionMnemonic : : AND , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 029 */ { VXInstructionMnemonic : : AND , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 02A */ { VXInstructionMnemonic : : AND , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 | IDF_OPERAND1_READWRITE } ,
/* 02B */ { VXInstructionMnemonic : : AND , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 02C */ { VXInstructionMnemonic : : AND , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 02D */ { VXInstructionMnemonic : : AND , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 02E */ { VXInstructionMnemonic : : AND , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_READWRITE } ,
/* 02F */ { VXInstructionMnemonic : : ANDNPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 030 */ { VXInstructionMnemonic : : ANDNPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 031 */ { VXInstructionMnemonic : : ANDPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 032 */ { VXInstructionMnemonic : : ANDPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 033 */ { VXInstructionMnemonic : : ARPL , { OPI_Ew , OPI_Gw , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_OPERAND1_WRITE } ,
/* 034 */ { VXInstructionMnemonic : : BLENDPD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 035 */ { VXInstructionMnemonic : : BLENDPS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 036 */ { VXInstructionMnemonic : : BLENDVPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 037 */ { VXInstructionMnemonic : : BLENDVPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 038 */ { VXInstructionMnemonic : : BOUND , { OPI_Gv , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 039 */ { VXInstructionMnemonic : : BSF , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 03A */ { VXInstructionMnemonic : : BSR , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 03B */ { VXInstructionMnemonic : : BSWAP , { OPI_R5y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 03C */ { VXInstructionMnemonic : : BSWAP , { OPI_R3y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 03D */ { VXInstructionMnemonic : : BSWAP , { OPI_R1y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 03E */ { VXInstructionMnemonic : : BSWAP , { OPI_R4y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 03F */ { VXInstructionMnemonic : : BSWAP , { OPI_R0y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 040 */ { VXInstructionMnemonic : : BSWAP , { OPI_R2y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 041 */ { VXInstructionMnemonic : : BSWAP , { OPI_R7y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 042 */ { VXInstructionMnemonic : : BSWAP , { OPI_R6y , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 043 */ { VXInstructionMnemonic : : BT , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 044 */ { VXInstructionMnemonic : : BT , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 045 */ { VXInstructionMnemonic : : BTC , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 046 */ { VXInstructionMnemonic : : BTC , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 047 */ { VXInstructionMnemonic : : BTR , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 048 */ { VXInstructionMnemonic : : BTR , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 049 */ { VXInstructionMnemonic : : BTS , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 04A */ { VXInstructionMnemonic : : BTS , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 04B */ { VXInstructionMnemonic : : CALL , { OPI_Eq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 04C */ { VXInstructionMnemonic : : CALL , { OPI_Fv , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 04D */ { VXInstructionMnemonic : : CALL , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 04E */ { VXInstructionMnemonic : : CALL , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_DEFAULT_64 } ,
/* 04F */ { VXInstructionMnemonic : : CALL , { OPI_Av , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 050 */ { VXInstructionMnemonic : : CBW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 051 */ { VXInstructionMnemonic : : CDQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 052 */ { VXInstructionMnemonic : : CDQE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
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/* 053 */ { VXInstructionMnemonic : : CLC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 054 */ { VXInstructionMnemonic : : CLD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 055 */ { VXInstructionMnemonic : : CLFLUSH , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
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/* 056 */ { VXInstructionMnemonic : : CLGI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 057 */ { VXInstructionMnemonic : : CLI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 058 */ { VXInstructionMnemonic : : CLTS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 059 */ { VXInstructionMnemonic : : CMC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 05A */ { VXInstructionMnemonic : : CMOVA , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 05B */ { VXInstructionMnemonic : : CMOVAE , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 05C */ { VXInstructionMnemonic : : CMOVB , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 05D */ { VXInstructionMnemonic : : CMOVBE , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 05E */ { VXInstructionMnemonic : : CMOVE , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 05F */ { VXInstructionMnemonic : : CMOVG , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 060 */ { VXInstructionMnemonic : : CMOVGE , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 061 */ { VXInstructionMnemonic : : CMOVL , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 062 */ { VXInstructionMnemonic : : CMOVLE , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 063 */ { VXInstructionMnemonic : : CMOVNE , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 064 */ { VXInstructionMnemonic : : CMOVNO , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 065 */ { VXInstructionMnemonic : : CMOVNP , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 066 */ { VXInstructionMnemonic : : CMOVNS , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 067 */ { VXInstructionMnemonic : : CMOVO , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 068 */ { VXInstructionMnemonic : : CMOVP , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 069 */ { VXInstructionMnemonic : : CMOVS , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 06A */ { VXInstructionMnemonic : : CMP , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 06B */ { VXInstructionMnemonic : : CMP , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 06C */ { VXInstructionMnemonic : : CMP , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 06D */ { VXInstructionMnemonic : : CMP , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 06E */ { VXInstructionMnemonic : : CMP , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 06F */ { VXInstructionMnemonic : : CMP , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 070 */ { VXInstructionMnemonic : : CMP , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , 0 } ,
/* 071 */ { VXInstructionMnemonic : : CMP , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 072 */ { VXInstructionMnemonic : : CMP , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 073 */ { VXInstructionMnemonic : : CMP , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 } ,
/* 074 */ { VXInstructionMnemonic : : CMPPD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 075 */ { VXInstructionMnemonic : : CMPPS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 076 */ { VXInstructionMnemonic : : CMPSB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 077 */ { VXInstructionMnemonic : : CMPSD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 078 */ { VXInstructionMnemonic : : CMPSD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 079 */ { VXInstructionMnemonic : : CMPSQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 07A */ { VXInstructionMnemonic : : CMPSS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 07B */ { VXInstructionMnemonic : : CMPSW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 07C */ { VXInstructionMnemonic : : CMPXCHG , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 07D */ { VXInstructionMnemonic : : CMPXCHG , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 07E */ { VXInstructionMnemonic : : CMPXCHG16B , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 07F */ { VXInstructionMnemonic : : CMPXCHG8B , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 080 */ { VXInstructionMnemonic : : CMPXCHG8B , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 081 */ { VXInstructionMnemonic : : COMISD , { OPI_Vsd , OPI_Wsd , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 082 */ { VXInstructionMnemonic : : COMISS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 083 */ { VXInstructionMnemonic : : CPUID , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 084 */ { VXInstructionMnemonic : : CQO , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 085 */ { VXInstructionMnemonic : : CRC32 , { OPI_Gy , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 086 */ { VXInstructionMnemonic : : CRC32 , { OPI_Gy , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 087 */ { VXInstructionMnemonic : : CVTDQ2PD , { OPI_V , OPI_Wdq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 088 */ { VXInstructionMnemonic : : CVTDQ2PS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 089 */ { VXInstructionMnemonic : : CVTPD2DQ , { OPI_Vdq , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 08A */ { VXInstructionMnemonic : : CVTPD2PI , { OPI_P , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 08B */ { VXInstructionMnemonic : : CVTPD2PS , { OPI_Vdq , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 08C */ { VXInstructionMnemonic : : CVTPI2PD , { OPI_V , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 08D */ { VXInstructionMnemonic : : CVTPI2PS , { OPI_V , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 08E */ { VXInstructionMnemonic : : CVTPS2DQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 08F */ { VXInstructionMnemonic : : CVTPS2PD , { OPI_V , OPI_Wdq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 090 */ { VXInstructionMnemonic : : CVTPS2PI , { OPI_P , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 091 */ { VXInstructionMnemonic : : CVTSD2SI , { OPI_Gy , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 092 */ { VXInstructionMnemonic : : CVTSD2SS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 093 */ { VXInstructionMnemonic : : CVTSI2SD , { OPI_V , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 094 */ { VXInstructionMnemonic : : CVTSI2SS , { OPI_V , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 095 */ { VXInstructionMnemonic : : CVTSS2SD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 096 */ { VXInstructionMnemonic : : CVTSS2SI , { OPI_Gy , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 097 */ { VXInstructionMnemonic : : CVTTPD2DQ , { OPI_Vdq , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 098 */ { VXInstructionMnemonic : : CVTTPD2PI , { OPI_P , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 099 */ { VXInstructionMnemonic : : CVTTPS2DQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 09A */ { VXInstructionMnemonic : : CVTTPS2PI , { OPI_P , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 09B */ { VXInstructionMnemonic : : CVTTSD2SI , { OPI_Gy , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 09C */ { VXInstructionMnemonic : : CVTTSS2SI , { OPI_Gy , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 09D */ { VXInstructionMnemonic : : CWD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 09E */ { VXInstructionMnemonic : : CWDE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
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/* 09F */ { VXInstructionMnemonic : : DAA , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
/* 0A0 */ { VXInstructionMnemonic : : DAS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
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/* 0A1 */ { VXInstructionMnemonic : : DEC , { OPI_R6z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0A2 */ { VXInstructionMnemonic : : DEC , { OPI_R5z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0A3 */ { VXInstructionMnemonic : : DEC , { OPI_R7z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0A4 */ { VXInstructionMnemonic : : DEC , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0A5 */ { VXInstructionMnemonic : : DEC , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0A6 */ { VXInstructionMnemonic : : DEC , { OPI_R1z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0A7 */ { VXInstructionMnemonic : : DEC , { OPI_R0z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0A8 */ { VXInstructionMnemonic : : DEC , { OPI_R2z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0A9 */ { VXInstructionMnemonic : : DEC , { OPI_R4z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0AA */ { VXInstructionMnemonic : : DEC , { OPI_R3z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 0AB */ { VXInstructionMnemonic : : DIV , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 0AC */ { VXInstructionMnemonic : : DIV , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 0AD */ { VXInstructionMnemonic : : DIVPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0AE */ { VXInstructionMnemonic : : DIVPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0AF */ { VXInstructionMnemonic : : DIVSD , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0B0 */ { VXInstructionMnemonic : : DIVSS , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0B1 */ { VXInstructionMnemonic : : DPPD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 0B2 */ { VXInstructionMnemonic : : DPPS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
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/* 0B3 */ { VXInstructionMnemonic : : EMMS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 0B4 */ { VXInstructionMnemonic : : ENTER , { OPI_Iw , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_DEFAULT_64 } ,
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/* 0B5 */ { VXInstructionMnemonic : : EXTRACTPS , { OPI_MdRy , OPI_V , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
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/* 0B6 */ { VXInstructionMnemonic : : F2XM1 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 0B7 */ { VXInstructionMnemonic : : FABS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 0B8 */ { VXInstructionMnemonic : : FADD , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0B9 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 0BA */ { VXInstructionMnemonic : : FADD , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 0BB */ { VXInstructionMnemonic : : FADD , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 0BC */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0BD */ { VXInstructionMnemonic : : FADD , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0BE */ { VXInstructionMnemonic : : FADD , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0BF */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C0 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C1 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C2 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C3 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C4 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C5 */ { VXInstructionMnemonic : : FADD , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C6 */ { VXInstructionMnemonic : : FADD , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C7 */ { VXInstructionMnemonic : : FADD , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C8 */ { VXInstructionMnemonic : : FADD , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0C9 */ { VXInstructionMnemonic : : FADD , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0CA */ { VXInstructionMnemonic : : FADDP , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0CB */ { VXInstructionMnemonic : : FADDP , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0CC */ { VXInstructionMnemonic : : FADDP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0CD */ { VXInstructionMnemonic : : FADDP , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0CE */ { VXInstructionMnemonic : : FADDP , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0CF */ { VXInstructionMnemonic : : FADDP , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D0 */ { VXInstructionMnemonic : : FADDP , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D1 */ { VXInstructionMnemonic : : FADDP , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 0D2 */ { VXInstructionMnemonic : : FBLD , { OPI_Mt , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 0D3 */ { VXInstructionMnemonic : : FBSTP , { OPI_Mt , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 0D4 */ { VXInstructionMnemonic : : FCHS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D5 */ { VXInstructionMnemonic : : FCLEX , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D6 */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D7 */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D8 */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0D9 */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0DA */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0DB */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0DC */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0DD */ { VXInstructionMnemonic : : FCMOVB , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0DE */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0DF */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E0 */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E1 */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E2 */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E3 */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E4 */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E5 */ { VXInstructionMnemonic : : FCMOVBE , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E6 */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E7 */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E8 */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0E9 */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0EA */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0EB */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0EC */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0ED */ { VXInstructionMnemonic : : FCMOVE , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0EE */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0EF */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F0 */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F1 */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F2 */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F3 */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F4 */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F5 */ { VXInstructionMnemonic : : FCMOVNB , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F6 */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F7 */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F8 */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0F9 */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0FA */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0FB */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0FC */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0FD */ { VXInstructionMnemonic : : FCMOVNBE , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0FE */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 0FF */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 100 */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 101 */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 102 */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 103 */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 104 */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 105 */ { VXInstructionMnemonic : : FCMOVNE , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 106 */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 107 */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 108 */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 109 */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 10A */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 10B */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 10C */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 10D */ { VXInstructionMnemonic : : FCMOVNU , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 10E */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 10F */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 110 */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 111 */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 112 */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 113 */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 114 */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 115 */ { VXInstructionMnemonic : : FCMOVU , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 116 */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 117 */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 118 */ { VXInstructionMnemonic : : FCOM , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 119 */ { VXInstructionMnemonic : : FCOM , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 11A */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 11B */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 11C */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 11D */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 11E */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 11F */ { VXInstructionMnemonic : : FCOM , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 120 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 121 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 122 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 123 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 124 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 125 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 126 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 127 */ { VXInstructionMnemonic : : FCOM2 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 128 */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 129 */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 12A */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 12B */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 12C */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 12D */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 12E */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 12F */ { VXInstructionMnemonic : : FCOMI , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 130 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 131 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 132 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 133 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 134 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 135 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 136 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 137 */ { VXInstructionMnemonic : : FCOMIP , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 138 */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 139 */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 13A */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 13B */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 13C */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 13D */ { VXInstructionMnemonic : : FCOMP , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 13E */ { VXInstructionMnemonic : : FCOMP , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 13F */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 140 */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 141 */ { VXInstructionMnemonic : : FCOMP , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 142 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 143 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 144 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 145 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 146 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 147 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 148 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 149 */ { VXInstructionMnemonic : : FCOMP3 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 14A */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 14B */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 14C */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 14D */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 14E */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 14F */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 150 */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 151 */ { VXInstructionMnemonic : : FCOMP5 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 152 */ { VXInstructionMnemonic : : FCOMPP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 153 */ { VXInstructionMnemonic : : FCOS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 154 */ { VXInstructionMnemonic : : FDECSTP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 155 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 156 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 157 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 158 */ { VXInstructionMnemonic : : FDIV , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 159 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 15A */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 15B */ { VXInstructionMnemonic : : FDIV , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 15C */ { VXInstructionMnemonic : : FDIV , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 15D */ { VXInstructionMnemonic : : FDIV , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 15E */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 15F */ { VXInstructionMnemonic : : FDIV , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 160 */ { VXInstructionMnemonic : : FDIV , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 161 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 162 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 163 */ { VXInstructionMnemonic : : FDIV , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 164 */ { VXInstructionMnemonic : : FDIV , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 165 */ { VXInstructionMnemonic : : FDIV , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 166 */ { VXInstructionMnemonic : : FDIV , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 167 */ { VXInstructionMnemonic : : FDIVP , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 168 */ { VXInstructionMnemonic : : FDIVP , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 169 */ { VXInstructionMnemonic : : FDIVP , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 16A */ { VXInstructionMnemonic : : FDIVP , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 16B */ { VXInstructionMnemonic : : FDIVP , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 16C */ { VXInstructionMnemonic : : FDIVP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 16D */ { VXInstructionMnemonic : : FDIVP , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 16E */ { VXInstructionMnemonic : : FDIVP , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 16F */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 170 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 171 */ { VXInstructionMnemonic : : FDIVR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 172 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 173 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 174 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 175 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 176 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 177 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 178 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 179 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 17A */ { VXInstructionMnemonic : : FDIVR , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 17B */ { VXInstructionMnemonic : : FDIVR , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 17C */ { VXInstructionMnemonic : : FDIVR , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 17D */ { VXInstructionMnemonic : : FDIVR , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 17E */ { VXInstructionMnemonic : : FDIVR , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 17F */ { VXInstructionMnemonic : : FDIVR , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 180 */ { VXInstructionMnemonic : : FDIVR , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 181 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 182 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 183 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 184 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 185 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 186 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 187 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 188 */ { VXInstructionMnemonic : : FDIVRP , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 189 */ { VXInstructionMnemonic : : FEMMS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 18A */ { VXInstructionMnemonic : : FFREE , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 18B */ { VXInstructionMnemonic : : FFREE , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 18C */ { VXInstructionMnemonic : : FFREE , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 18D */ { VXInstructionMnemonic : : FFREE , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 18E */ { VXInstructionMnemonic : : FFREE , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 18F */ { VXInstructionMnemonic : : FFREE , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 190 */ { VXInstructionMnemonic : : FFREE , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 191 */ { VXInstructionMnemonic : : FFREE , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 192 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 193 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 194 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 195 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 196 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 197 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 198 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 199 */ { VXInstructionMnemonic : : FFREEP , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 19A */ { VXInstructionMnemonic : : FIADD , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 19B */ { VXInstructionMnemonic : : FIADD , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 19C */ { VXInstructionMnemonic : : FICOM , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 19D */ { VXInstructionMnemonic : : FICOM , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 19E */ { VXInstructionMnemonic : : FICOMP , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 19F */ { VXInstructionMnemonic : : FICOMP , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A0 */ { VXInstructionMnemonic : : FIDIV , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A1 */ { VXInstructionMnemonic : : FIDIV , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A2 */ { VXInstructionMnemonic : : FIDIVR , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A3 */ { VXInstructionMnemonic : : FIDIVR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A4 */ { VXInstructionMnemonic : : FILD , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A5 */ { VXInstructionMnemonic : : FILD , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A6 */ { VXInstructionMnemonic : : FILD , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A7 */ { VXInstructionMnemonic : : FIMUL , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1A8 */ { VXInstructionMnemonic : : FIMUL , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 1A9 */ { VXInstructionMnemonic : : FINCSTP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1AA */ { VXInstructionMnemonic : : FIST , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1AB */ { VXInstructionMnemonic : : FIST , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1AC */ { VXInstructionMnemonic : : FISTP , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1AD */ { VXInstructionMnemonic : : FISTP , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1AE */ { VXInstructionMnemonic : : FISTP , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1AF */ { VXInstructionMnemonic : : FISTTP , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B0 */ { VXInstructionMnemonic : : FISTTP , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B1 */ { VXInstructionMnemonic : : FISTTP , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B2 */ { VXInstructionMnemonic : : FISUB , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B3 */ { VXInstructionMnemonic : : FISUB , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B4 */ { VXInstructionMnemonic : : FISUBR , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B5 */ { VXInstructionMnemonic : : FISUBR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1B6 */ { VXInstructionMnemonic : : FLD , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1B7 */ { VXInstructionMnemonic : : FLD , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1B8 */ { VXInstructionMnemonic : : FLD , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1B9 */ { VXInstructionMnemonic : : FLD , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1BA */ { VXInstructionMnemonic : : FLD , { OPI_Mt , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1BB */ { VXInstructionMnemonic : : FLD , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1BC */ { VXInstructionMnemonic : : FLD , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1BD */ { VXInstructionMnemonic : : FLD , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1BE */ { VXInstructionMnemonic : : FLD , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1BF */ { VXInstructionMnemonic : : FLD , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1C0 */ { VXInstructionMnemonic : : FLD , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1C1 */ { VXInstructionMnemonic : : FLD1 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1C2 */ { VXInstructionMnemonic : : FLDCW , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1C3 */ { VXInstructionMnemonic : : FLDENV , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 1C4 */ { VXInstructionMnemonic : : FLDL2E , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1C5 */ { VXInstructionMnemonic : : FLDL2T , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1C6 */ { VXInstructionMnemonic : : FLDLG2 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1C7 */ { VXInstructionMnemonic : : FLDLN2 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1C8 */ { VXInstructionMnemonic : : FLDPI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1C9 */ { VXInstructionMnemonic : : FLDZ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1CA */ { VXInstructionMnemonic : : FMUL , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1CB */ { VXInstructionMnemonic : : FMUL , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1CC */ { VXInstructionMnemonic : : FMUL , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1CD */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1CE */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1CF */ { VXInstructionMnemonic : : FMUL , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1D0 */ { VXInstructionMnemonic : : FMUL , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D1 */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D2 */ { VXInstructionMnemonic : : FMUL , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1D3 */ { VXInstructionMnemonic : : FMUL , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D4 */ { VXInstructionMnemonic : : FMUL , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D5 */ { VXInstructionMnemonic : : FMUL , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D6 */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D7 */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D8 */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1D9 */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1DA */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1DB */ { VXInstructionMnemonic : : FMUL , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1DC */ { VXInstructionMnemonic : : FMULP , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1DD */ { VXInstructionMnemonic : : FMULP , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1DE */ { VXInstructionMnemonic : : FMULP , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1DF */ { VXInstructionMnemonic : : FMULP , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E0 */ { VXInstructionMnemonic : : FMULP , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E1 */ { VXInstructionMnemonic : : FMULP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E2 */ { VXInstructionMnemonic : : FMULP , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E3 */ { VXInstructionMnemonic : : FMULP , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1E4 */ { VXInstructionMnemonic : : FNDISI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E5 */ { VXInstructionMnemonic : : FNENI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E6 */ { VXInstructionMnemonic : : FNINIT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E7 */ { VXInstructionMnemonic : : FNOP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1E8 */ { VXInstructionMnemonic : : FNSAVE , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1E9 */ { VXInstructionMnemonic : : FNSETPM , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1EA */ { VXInstructionMnemonic : : FNSTCW , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1EB */ { VXInstructionMnemonic : : FNSTENV , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1EC */ { VXInstructionMnemonic : : FNSTSW , { OPI_AX , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1ED */ { VXInstructionMnemonic : : FNSTSW , { OPI_Mw , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1EE */ { VXInstructionMnemonic : : FPATAN , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1EF */ { VXInstructionMnemonic : : FPREM , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F0 */ { VXInstructionMnemonic : : FPREM1 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F1 */ { VXInstructionMnemonic : : FPTAN , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F2 */ { VXInstructionMnemonic : : FRNDINT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F3 */ { VXInstructionMnemonic : : FRSTOR , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1F4 */ { VXInstructionMnemonic : : FRSTPM , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F5 */ { VXInstructionMnemonic : : FSCALE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F6 */ { VXInstructionMnemonic : : FSIN , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F7 */ { VXInstructionMnemonic : : FSINCOS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F8 */ { VXInstructionMnemonic : : FSQRT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1F9 */ { VXInstructionMnemonic : : FST , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1FA */ { VXInstructionMnemonic : : FST , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 1FB */ { VXInstructionMnemonic : : FST , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1FC */ { VXInstructionMnemonic : : FST , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1FD */ { VXInstructionMnemonic : : FST , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 1FE */ { VXInstructionMnemonic : : FST , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 1FF */ { VXInstructionMnemonic : : FST , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 200 */ { VXInstructionMnemonic : : FST , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 201 */ { VXInstructionMnemonic : : FST , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 202 */ { VXInstructionMnemonic : : FST , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 203 */ { VXInstructionMnemonic : : FSTP , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 204 */ { VXInstructionMnemonic : : FSTP , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 205 */ { VXInstructionMnemonic : : FSTP , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 206 */ { VXInstructionMnemonic : : FSTP , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 207 */ { VXInstructionMnemonic : : FSTP , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 208 */ { VXInstructionMnemonic : : FSTP , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 209 */ { VXInstructionMnemonic : : FSTP , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 20A */ { VXInstructionMnemonic : : FSTP , { OPI_Mt , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 20B */ { VXInstructionMnemonic : : FSTP , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 20C */ { VXInstructionMnemonic : : FSTP , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 20D */ { VXInstructionMnemonic : : FSTP , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 20E */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 20F */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 210 */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 211 */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 212 */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 213 */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 214 */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 215 */ { VXInstructionMnemonic : : FSTP1 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 216 */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 217 */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 218 */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 219 */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 21A */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 21B */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 21C */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 21D */ { VXInstructionMnemonic : : FSTP8 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 21E */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 21F */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 220 */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 221 */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 222 */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 223 */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 224 */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 225 */ { VXInstructionMnemonic : : FSTP9 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 226 */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 227 */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 228 */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 229 */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 22A */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 22B */ { VXInstructionMnemonic : : FSUB , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 22C */ { VXInstructionMnemonic : : FSUB , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 22D */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 22E */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 22F */ { VXInstructionMnemonic : : FSUB , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 230 */ { VXInstructionMnemonic : : FSUB , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 231 */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 232 */ { VXInstructionMnemonic : : FSUB , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 233 */ { VXInstructionMnemonic : : FSUB , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 234 */ { VXInstructionMnemonic : : FSUB , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 235 */ { VXInstructionMnemonic : : FSUB , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 236 */ { VXInstructionMnemonic : : FSUB , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 237 */ { VXInstructionMnemonic : : FSUB , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 238 */ { VXInstructionMnemonic : : FSUBP , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 239 */ { VXInstructionMnemonic : : FSUBP , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 23A */ { VXInstructionMnemonic : : FSUBP , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 23B */ { VXInstructionMnemonic : : FSUBP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 23C */ { VXInstructionMnemonic : : FSUBP , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 23D */ { VXInstructionMnemonic : : FSUBP , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 23E */ { VXInstructionMnemonic : : FSUBP , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 23F */ { VXInstructionMnemonic : : FSUBP , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 240 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 241 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 242 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 243 */ { VXInstructionMnemonic : : FSUBR , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
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/* 244 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 245 */ { VXInstructionMnemonic : : FSUBR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 246 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 247 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 248 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 249 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 24A */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 24B */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 24C */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 24D */ { VXInstructionMnemonic : : FSUBR , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 24E */ { VXInstructionMnemonic : : FSUBR , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 24F */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 250 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 251 */ { VXInstructionMnemonic : : FSUBR , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 252 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST5 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 253 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST4 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 254 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST7 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 255 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST6 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 256 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST2 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 257 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST3 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 258 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 259 */ { VXInstructionMnemonic : : FSUBRP , { OPI_ST1 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 25A */ { VXInstructionMnemonic : : FTST , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 25B */ { VXInstructionMnemonic : : FUCOM , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 25C */ { VXInstructionMnemonic : : FUCOM , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 25D */ { VXInstructionMnemonic : : FUCOM , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 25E */ { VXInstructionMnemonic : : FUCOM , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 25F */ { VXInstructionMnemonic : : FUCOM , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 260 */ { VXInstructionMnemonic : : FUCOM , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 261 */ { VXInstructionMnemonic : : FUCOM , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 262 */ { VXInstructionMnemonic : : FUCOM , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 263 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
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/* 264 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 265 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 266 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 267 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 268 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 269 */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 26A */ { VXInstructionMnemonic : : FUCOMI , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 26B */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 26C */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 26D */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 26E */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 26F */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 270 */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 271 */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 272 */ { VXInstructionMnemonic : : FUCOMIP , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 273 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 274 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 275 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 276 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 277 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 278 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 279 */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 27A */ { VXInstructionMnemonic : : FUCOMP , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 27B */ { VXInstructionMnemonic : : FUCOMPP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 27C */ { VXInstructionMnemonic : : FXAM , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 27D */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST4 , OPI_NONE , OPI_NONE } , 0 } ,
/* 27E */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST5 , OPI_NONE , OPI_NONE } , 0 } ,
/* 27F */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST6 , OPI_NONE , OPI_NONE } , 0 } ,
/* 280 */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST3 , OPI_NONE , OPI_NONE } , 0 } ,
/* 281 */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST0 , OPI_NONE , OPI_NONE } , 0 } ,
/* 282 */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST1 , OPI_NONE , OPI_NONE } , 0 } ,
/* 283 */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST2 , OPI_NONE , OPI_NONE } , 0 } ,
/* 284 */ { VXInstructionMnemonic : : FXCH , { OPI_ST0 , OPI_ST7 , OPI_NONE , OPI_NONE } , 0 } ,
/* 285 */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 286 */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 287 */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 288 */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 289 */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 28A */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 28B */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 28C */ { VXInstructionMnemonic : : FXCH4 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 28D */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST2 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 28E */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST3 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 28F */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST0 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 290 */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST1 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 291 */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST6 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 292 */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST7 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 293 */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST4 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 294 */ { VXInstructionMnemonic : : FXCH7 , { OPI_ST5 , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 295 */ { VXInstructionMnemonic : : FXRSTOR , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 296 */ { VXInstructionMnemonic : : FXSAVE , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 297 */ { VXInstructionMnemonic : : FXTRACT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 298 */ { VXInstructionMnemonic : : FYL2X , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 299 */ { VXInstructionMnemonic : : FYL2XP1 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 29A */ { VXInstructionMnemonic : : GETSEC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 29B */ { VXInstructionMnemonic : : HADDPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 29C */ { VXInstructionMnemonic : : HADDPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 29D */ { VXInstructionMnemonic : : HLT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 29E */ { VXInstructionMnemonic : : HSUBPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 29F */ { VXInstructionMnemonic : : HSUBPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2A0 */ { VXInstructionMnemonic : : IDIV , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2A1 */ { VXInstructionMnemonic : : IDIV , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2A2 */ { VXInstructionMnemonic : : IMUL , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2A3 */ { VXInstructionMnemonic : : IMUL , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2A4 */ { VXInstructionMnemonic : : IMUL , { OPI_Gv , OPI_Ev , OPI_Iz , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2A5 */ { VXInstructionMnemonic : : IMUL , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2A6 */ { VXInstructionMnemonic : : IMUL , { OPI_Gv , OPI_Ev , OPI_sIb , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2A7 */ { VXInstructionMnemonic : : IN , { OPI_AL , OPI_DX , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 2A8 */ { VXInstructionMnemonic : : IN , { OPI_eAX , OPI_DX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_WRITE } ,
/* 2A9 */ { VXInstructionMnemonic : : IN , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 2AA */ { VXInstructionMnemonic : : IN , { OPI_eAX , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_WRITE } ,
/* 2AB */ { VXInstructionMnemonic : : INC , { OPI_R0z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2AC */ { VXInstructionMnemonic : : INC , { OPI_R1z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2AD */ { VXInstructionMnemonic : : INC , { OPI_R7z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2AE */ { VXInstructionMnemonic : : INC , { OPI_R6z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2AF */ { VXInstructionMnemonic : : INC , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2B0 */ { VXInstructionMnemonic : : INC , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 2B1 */ { VXInstructionMnemonic : : INC , { OPI_R3z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2B2 */ { VXInstructionMnemonic : : INC , { OPI_R2z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2B3 */ { VXInstructionMnemonic : : INC , { OPI_R4z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2B4 */ { VXInstructionMnemonic : : INC , { OPI_R5z , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_READWRITE } ,
/* 2B5 */ { VXInstructionMnemonic : : INSB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 2B6 */ { VXInstructionMnemonic : : INSD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 2B7 */ { VXInstructionMnemonic : : INSERTPS , { OPI_V , OPI_Md , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 2B8 */ { VXInstructionMnemonic : : INSW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 2B9 */ { VXInstructionMnemonic : : INT , { OPI_Ib , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2BA */ { VXInstructionMnemonic : : INT1 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2BB */ { VXInstructionMnemonic : : INT3 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2BC */ { VXInstructionMnemonic : : INTO , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
/* 2BD */ { VXInstructionMnemonic : : INVD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2BE */ { VXInstructionMnemonic : : INVEPT , { OPI_Gd , OPI_Mo , OPI_NONE , OPI_NONE } , 0 } ,
/* 2BF */ { VXInstructionMnemonic : : INVEPT , { OPI_Gq , OPI_Mo , OPI_NONE , OPI_NONE } , 0 } ,
/* 2C0 */ { VXInstructionMnemonic : : INVLPG , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2C1 */ { VXInstructionMnemonic : : INVLPGA , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 2C2 */ { VXInstructionMnemonic : : INVVPID , { OPI_Gq , OPI_Mo , OPI_NONE , OPI_NONE } , 0 } ,
/* 2C3 */ { VXInstructionMnemonic : : INVVPID , { OPI_Gd , OPI_Mo , OPI_NONE , OPI_NONE } , 0 } ,
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/* 2C4 */ { VXInstructionMnemonic : : IRETD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 2C5 */ { VXInstructionMnemonic : : IRETQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 2C6 */ { VXInstructionMnemonic : : IRETW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
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/* 2C7 */ { VXInstructionMnemonic : : JA , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2C8 */ { VXInstructionMnemonic : : JA , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2C9 */ { VXInstructionMnemonic : : JB , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2CA */ { VXInstructionMnemonic : : JB , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2CB */ { VXInstructionMnemonic : : JBE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2CC */ { VXInstructionMnemonic : : JBE , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2CD */ { VXInstructionMnemonic : : JCXZ , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX } ,
/* 2CE */ { VXInstructionMnemonic : : JE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2CF */ { VXInstructionMnemonic : : JE , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2D0 */ { VXInstructionMnemonic : : JECXZ , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX } ,
/* 2D1 */ { VXInstructionMnemonic : : JG , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2D2 */ { VXInstructionMnemonic : : JG , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2D3 */ { VXInstructionMnemonic : : JGE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2D4 */ { VXInstructionMnemonic : : JGE , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2D5 */ { VXInstructionMnemonic : : JL , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2D6 */ { VXInstructionMnemonic : : JL , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2D7 */ { VXInstructionMnemonic : : JLE , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2D8 */ { VXInstructionMnemonic : : JLE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2D9 */ { VXInstructionMnemonic : : JMP , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 2DA */ { VXInstructionMnemonic : : JMP , { OPI_Fv , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2DB */ { VXInstructionMnemonic : : JMP , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_DEFAULT_64 } ,
/* 2DC */ { VXInstructionMnemonic : : JMP , { OPI_Av , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 2DD */ { VXInstructionMnemonic : : JMP , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_DEFAULT_64 } ,
/* 2DE */ { VXInstructionMnemonic : : JNB , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2DF */ { VXInstructionMnemonic : : JNB , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
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/* 2E0 */ { VXInstructionMnemonic : : JNE , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2E1 */ { VXInstructionMnemonic : : JNE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2E2 */ { VXInstructionMnemonic : : JNO , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2E3 */ { VXInstructionMnemonic : : JNO , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2E4 */ { VXInstructionMnemonic : : JNP , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2E5 */ { VXInstructionMnemonic : : JNP , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2E6 */ { VXInstructionMnemonic : : JNS , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2E7 */ { VXInstructionMnemonic : : JNS , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2E8 */ { VXInstructionMnemonic : : JO , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2E9 */ { VXInstructionMnemonic : : JO , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2EA */ { VXInstructionMnemonic : : JP , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2EB */ { VXInstructionMnemonic : : JP , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2EC */ { VXInstructionMnemonic : : JRCXZ , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX } ,
/* 2ED */ { VXInstructionMnemonic : : JS , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2EE */ { VXInstructionMnemonic : : JS , { OPI_Jz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 2EF */ { VXInstructionMnemonic : : LAHF , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2F0 */ { VXInstructionMnemonic : : LAR , { OPI_Gv , OPI_Ew , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 2F1 */ { VXInstructionMnemonic : : LDDQU , { OPI_V , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 2F2 */ { VXInstructionMnemonic : : LDMXCSR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2F3 */ { VXInstructionMnemonic : : LDS , { OPI_Gv , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_WRITE } ,
/* 2F4 */ { VXInstructionMnemonic : : LEA , { OPI_Gv , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 2F5 */ { VXInstructionMnemonic : : LEAVE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 2F6 */ { VXInstructionMnemonic : : LES , { OPI_Gv , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_OPERAND1_WRITE } ,
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/* 2F7 */ { VXInstructionMnemonic : : LFENCE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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/* 2F8 */ { VXInstructionMnemonic : : LFS , { OPI_Gz , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 2F9 */ { VXInstructionMnemonic : : LGDT , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2FA */ { VXInstructionMnemonic : : LGS , { OPI_Gz , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 2FB */ { VXInstructionMnemonic : : LIDT , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2FC */ { VXInstructionMnemonic : : LLDT , { OPI_Ew , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2FD */ { VXInstructionMnemonic : : LMSW , { OPI_Ew , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2FE */ { VXInstructionMnemonic : : LMSW , { OPI_Ew , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 2FF */ { VXInstructionMnemonic : : LOCK , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 300 */ { VXInstructionMnemonic : : LODSB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 301 */ { VXInstructionMnemonic : : LODSD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 302 */ { VXInstructionMnemonic : : LODSQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 303 */ { VXInstructionMnemonic : : LODSW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 304 */ { VXInstructionMnemonic : : LOOP , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 305 */ { VXInstructionMnemonic : : LOOPE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 306 */ { VXInstructionMnemonic : : LOOPNE , { OPI_Jb , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 307 */ { VXInstructionMnemonic : : LSL , { OPI_Gv , OPI_Ew , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 308 */ { VXInstructionMnemonic : : LSS , { OPI_Gv , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 309 */ { VXInstructionMnemonic : : LTR , { OPI_Ew , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 30A */ { VXInstructionMnemonic : : MASKMOVDQU , { OPI_V , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 30B */ { VXInstructionMnemonic : : MASKMOVQ , { OPI_P , OPI_N , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 30C */ { VXInstructionMnemonic : : MAXPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 30D */ { VXInstructionMnemonic : : MAXPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 30E */ { VXInstructionMnemonic : : MAXSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 30F */ { VXInstructionMnemonic : : MAXSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 310 */ { VXInstructionMnemonic : : MFENCE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 311 */ { VXInstructionMnemonic : : MINPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 312 */ { VXInstructionMnemonic : : MINPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 313 */ { VXInstructionMnemonic : : MINSD , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 314 */ { VXInstructionMnemonic : : MINSS , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 315 */ { VXInstructionMnemonic : : MONITOR , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 316 */ { VXInstructionMnemonic : : MONTMUL , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 317 */ { VXInstructionMnemonic : : MOV , { OPI_R0b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 318 */ { VXInstructionMnemonic : : MOV , { OPI_R2b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 319 */ { VXInstructionMnemonic : : MOV , { OPI_R3b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 31A */ { VXInstructionMnemonic : : MOV , { OPI_R1b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 31B */ { VXInstructionMnemonic : : MOV , { OPI_AL , OPI_Ob , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 31C */ { VXInstructionMnemonic : : MOV , { OPI_S , OPI_MwRv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 31D */ { VXInstructionMnemonic : : MOV , { OPI_MwRv , OPI_S , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 31E */ { VXInstructionMnemonic : : MOV , { OPI_Ov , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_WRITE } ,
/* 31F */ { VXInstructionMnemonic : : MOV , { OPI_Ob , OPI_AL , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 320 */ { VXInstructionMnemonic : : MOV , { OPI_rAX , OPI_Ov , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_WRITE } ,
/* 321 */ { VXInstructionMnemonic : : MOV , { OPI_R4b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 322 */ { VXInstructionMnemonic : : MOV , { OPI_R7v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 323 */ { VXInstructionMnemonic : : MOV , { OPI_R6v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 324 */ { VXInstructionMnemonic : : MOV , { OPI_R5v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 325 */ { VXInstructionMnemonic : : MOV , { OPI_R , OPI_C , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 326 */ { VXInstructionMnemonic : : MOV , { OPI_D , OPI_R , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 327 */ { VXInstructionMnemonic : : MOV , { OPI_C , OPI_R , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 328 */ { VXInstructionMnemonic : : MOV , { OPI_R , OPI_D , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 329 */ { VXInstructionMnemonic : : MOV , { OPI_R4v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 32A */ { VXInstructionMnemonic : : MOV , { OPI_R7b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 32B */ { VXInstructionMnemonic : : MOV , { OPI_R6b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 32C */ { VXInstructionMnemonic : : MOV , { OPI_R5b , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 32D */ { VXInstructionMnemonic : : MOV , { OPI_R0v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 32E */ { VXInstructionMnemonic : : MOV , { OPI_R3v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 32F */ { VXInstructionMnemonic : : MOV , { OPI_R2v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 330 */ { VXInstructionMnemonic : : MOV , { OPI_R1v , OPI_Iv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 331 */ { VXInstructionMnemonic : : MOV , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 332 */ { VXInstructionMnemonic : : MOV , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 333 */ { VXInstructionMnemonic : : MOV , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 334 */ { VXInstructionMnemonic : : MOV , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 335 */ { VXInstructionMnemonic : : MOV , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 336 */ { VXInstructionMnemonic : : MOV , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 337 */ { VXInstructionMnemonic : : MOVAPD , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 338 */ { VXInstructionMnemonic : : MOVAPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 339 */ { VXInstructionMnemonic : : MOVAPS , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 33A */ { VXInstructionMnemonic : : MOVAPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 33B */ { VXInstructionMnemonic : : MOVBE , { OPI_Gv , OPI_Mv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 33C */ { VXInstructionMnemonic : : MOVBE , { OPI_Mv , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 33D */ { VXInstructionMnemonic : : MOVD , { OPI_P , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 33E */ { VXInstructionMnemonic : : MOVD , { OPI_Ey , OPI_P , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 33F */ { VXInstructionMnemonic : : MOVD , { OPI_Ey , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 340 */ { VXInstructionMnemonic : : MOVD , { OPI_Ey , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 341 */ { VXInstructionMnemonic : : MOVD , { OPI_V , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 342 */ { VXInstructionMnemonic : : MOVD , { OPI_V , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 343 */ { VXInstructionMnemonic : : MOVD , { OPI_P , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 344 */ { VXInstructionMnemonic : : MOVD , { OPI_Ey , OPI_P , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 345 */ { VXInstructionMnemonic : : MOVDDUP , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 346 */ { VXInstructionMnemonic : : MOVDDUP , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 347 */ { VXInstructionMnemonic : : MOVDQ2Q , { OPI_P , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 348 */ { VXInstructionMnemonic : : MOVDQA , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 349 */ { VXInstructionMnemonic : : MOVDQA , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 34A */ { VXInstructionMnemonic : : MOVDQU , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 34B */ { VXInstructionMnemonic : : MOVDQU , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 34C */ { VXInstructionMnemonic : : MOVHLPS , { OPI_V , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 34D */ { VXInstructionMnemonic : : MOVHPD , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 34E */ { VXInstructionMnemonic : : MOVHPD , { OPI_V , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 34F */ { VXInstructionMnemonic : : MOVHPS , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 350 */ { VXInstructionMnemonic : : MOVHPS , { OPI_V , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 351 */ { VXInstructionMnemonic : : MOVLHPS , { OPI_V , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 352 */ { VXInstructionMnemonic : : MOVLPD , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 353 */ { VXInstructionMnemonic : : MOVLPD , { OPI_V , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 354 */ { VXInstructionMnemonic : : MOVLPS , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 355 */ { VXInstructionMnemonic : : MOVLPS , { OPI_V , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 356 */ { VXInstructionMnemonic : : MOVMSKPD , { OPI_Gd , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 357 */ { VXInstructionMnemonic : : MOVMSKPS , { OPI_Gd , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 358 */ { VXInstructionMnemonic : : MOVNTDQ , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 359 */ { VXInstructionMnemonic : : MOVNTDQA , { OPI_V , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 35A */ { VXInstructionMnemonic : : MOVNTI , { OPI_M , OPI_Gy , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 35B */ { VXInstructionMnemonic : : MOVNTPD , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 35C */ { VXInstructionMnemonic : : MOVNTPS , { OPI_M , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 35D */ { VXInstructionMnemonic : : MOVNTQ , { OPI_M , OPI_P , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 35E */ { VXInstructionMnemonic : : MOVQ , { OPI_P , OPI_Eq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 35F */ { VXInstructionMnemonic : : MOVQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 360 */ { VXInstructionMnemonic : : MOVQ , { OPI_Eq , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 361 */ { VXInstructionMnemonic : : MOVQ , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 362 */ { VXInstructionMnemonic : : MOVQ , { OPI_Q , OPI_P , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 363 */ { VXInstructionMnemonic : : MOVQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 364 */ { VXInstructionMnemonic : : MOVQ , { OPI_V , OPI_Eq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 365 */ { VXInstructionMnemonic : : MOVQ , { OPI_Eq , OPI_P , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 366 */ { VXInstructionMnemonic : : MOVQ2DQ , { OPI_V , OPI_N , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_OPERAND1_WRITE } ,
/* 367 */ { VXInstructionMnemonic : : MOVSB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_OPERAND1_WRITE } ,
/* 368 */ { VXInstructionMnemonic : : MOVSD , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 369 */ { VXInstructionMnemonic : : MOVSD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_WRITE } ,
/* 36A */ { VXInstructionMnemonic : : MOVSD , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 36B */ { VXInstructionMnemonic : : MOVSHDUP , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 36C */ { VXInstructionMnemonic : : MOVSHDUP , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 36D */ { VXInstructionMnemonic : : MOVSLDUP , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 36E */ { VXInstructionMnemonic : : MOVSLDUP , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 36F */ { VXInstructionMnemonic : : MOVSQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_WRITE } ,
/* 370 */ { VXInstructionMnemonic : : MOVSS , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 371 */ { VXInstructionMnemonic : : MOVSS , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 372 */ { VXInstructionMnemonic : : MOVSW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_WRITE } ,
/* 373 */ { VXInstructionMnemonic : : MOVSX , { OPI_Gv , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 374 */ { VXInstructionMnemonic : : MOVSX , { OPI_Gy , OPI_Ew , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 375 */ { VXInstructionMnemonic : : MOVSXD , { OPI_Gq , OPI_Ed , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 376 */ { VXInstructionMnemonic : : MOVUPD , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 377 */ { VXInstructionMnemonic : : MOVUPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 378 */ { VXInstructionMnemonic : : MOVUPS , { OPI_W , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 379 */ { VXInstructionMnemonic : : MOVUPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 37A */ { VXInstructionMnemonic : : MOVZX , { OPI_Gy , OPI_Ew , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 37B */ { VXInstructionMnemonic : : MOVZX , { OPI_Gv , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 37C */ { VXInstructionMnemonic : : MPSADBW , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 37D */ { VXInstructionMnemonic : : MUL , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 37E */ { VXInstructionMnemonic : : MUL , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 37F */ { VXInstructionMnemonic : : MULPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 380 */ { VXInstructionMnemonic : : MULPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 381 */ { VXInstructionMnemonic : : MULSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 382 */ { VXInstructionMnemonic : : MULSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 383 */ { VXInstructionMnemonic : : MWAIT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 384 */ { VXInstructionMnemonic : : NEG , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 385 */ { VXInstructionMnemonic : : NEG , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 386 */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 387 */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 388 */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 389 */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 38A */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 38B */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 38C */ { VXInstructionMnemonic : : NOP , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 38D */ { VXInstructionMnemonic : : NOT , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 38E */ { VXInstructionMnemonic : : NOT , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 38F */ { VXInstructionMnemonic : : OR , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_READWRITE } ,
/* 390 */ { VXInstructionMnemonic : : OR , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 391 */ { VXInstructionMnemonic : : OR , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 392 */ { VXInstructionMnemonic : : OR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 393 */ { VXInstructionMnemonic : : OR , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 394 */ { VXInstructionMnemonic : : OR , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 395 */ { VXInstructionMnemonic : : OR , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 396 */ { VXInstructionMnemonic : : OR , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 397 */ { VXInstructionMnemonic : : OR , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 398 */ { VXInstructionMnemonic : : OR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 399 */ { VXInstructionMnemonic : : ORPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 39A */ { VXInstructionMnemonic : : ORPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 39B */ { VXInstructionMnemonic : : OUT , { OPI_DX , OPI_AL , OPI_NONE , OPI_NONE } , 0 } ,
/* 39C */ { VXInstructionMnemonic : : OUT , { OPI_DX , OPI_eAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 39D */ { VXInstructionMnemonic : : OUT , { OPI_Ib , OPI_AL , OPI_NONE , OPI_NONE } , 0 } ,
/* 39E */ { VXInstructionMnemonic : : OUT , { OPI_Ib , OPI_eAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 39F */ { VXInstructionMnemonic : : OUTSB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 3A0 */ { VXInstructionMnemonic : : OUTSD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 3A1 */ { VXInstructionMnemonic : : OUTSW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 3A2 */ { VXInstructionMnemonic : : PABSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3A3 */ { VXInstructionMnemonic : : PABSB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3A4 */ { VXInstructionMnemonic : : PABSD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3A5 */ { VXInstructionMnemonic : : PABSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3A6 */ { VXInstructionMnemonic : : PABSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3A7 */ { VXInstructionMnemonic : : PABSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3A8 */ { VXInstructionMnemonic : : PACKSSDW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3A9 */ { VXInstructionMnemonic : : PACKSSDW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3AA */ { VXInstructionMnemonic : : PACKSSWB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3AB */ { VXInstructionMnemonic : : PACKSSWB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3AC */ { VXInstructionMnemonic : : PACKUSDW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3AD */ { VXInstructionMnemonic : : PACKUSWB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3AE */ { VXInstructionMnemonic : : PACKUSWB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3AF */ { VXInstructionMnemonic : : PADDB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B0 */ { VXInstructionMnemonic : : PADDB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B1 */ { VXInstructionMnemonic : : PADDD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B2 */ { VXInstructionMnemonic : : PADDD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B3 */ { VXInstructionMnemonic : : PADDQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B4 */ { VXInstructionMnemonic : : PADDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B5 */ { VXInstructionMnemonic : : PADDSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B6 */ { VXInstructionMnemonic : : PADDSB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B7 */ { VXInstructionMnemonic : : PADDSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B8 */ { VXInstructionMnemonic : : PADDSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3B9 */ { VXInstructionMnemonic : : PADDUSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3BA */ { VXInstructionMnemonic : : PADDUSB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3BB */ { VXInstructionMnemonic : : PADDUSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3BC */ { VXInstructionMnemonic : : PADDUSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3BD */ { VXInstructionMnemonic : : PADDW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3BE */ { VXInstructionMnemonic : : PADDW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3BF */ { VXInstructionMnemonic : : PALIGNR , { OPI_P , OPI_Q , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C0 */ { VXInstructionMnemonic : : PALIGNR , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C1 */ { VXInstructionMnemonic : : PAND , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C2 */ { VXInstructionMnemonic : : PAND , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C3 */ { VXInstructionMnemonic : : PANDN , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C4 */ { VXInstructionMnemonic : : PANDN , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C5 */ { VXInstructionMnemonic : : PAVGB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C6 */ { VXInstructionMnemonic : : PAVGB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C7 */ { VXInstructionMnemonic : : PAVGUSB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C8 */ { VXInstructionMnemonic : : PAVGW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3C9 */ { VXInstructionMnemonic : : PAVGW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3CA */ { VXInstructionMnemonic : : PBLENDVB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3CB */ { VXInstructionMnemonic : : PBLENDW , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3CC */ { VXInstructionMnemonic : : PCLMULQDQ , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3CD */ { VXInstructionMnemonic : : PCMPEQB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3CE */ { VXInstructionMnemonic : : PCMPEQB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3CF */ { VXInstructionMnemonic : : PCMPEQD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D0 */ { VXInstructionMnemonic : : PCMPEQD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D1 */ { VXInstructionMnemonic : : PCMPEQQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 3D2 */ { VXInstructionMnemonic : : PCMPEQW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D3 */ { VXInstructionMnemonic : : PCMPEQW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D4 */ { VXInstructionMnemonic : : PCMPESTRI , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 3D5 */ { VXInstructionMnemonic : : PCMPESTRM , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 3D6 */ { VXInstructionMnemonic : : PCMPGTB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D7 */ { VXInstructionMnemonic : : PCMPGTB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D8 */ { VXInstructionMnemonic : : PCMPGTD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3D9 */ { VXInstructionMnemonic : : PCMPGTD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3DA */ { VXInstructionMnemonic : : PCMPGTQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 3DB */ { VXInstructionMnemonic : : PCMPGTW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3DC */ { VXInstructionMnemonic : : PCMPGTW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3DD */ { VXInstructionMnemonic : : PCMPISTRI , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 3DE */ { VXInstructionMnemonic : : PCMPISTRM , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 3DF */ { VXInstructionMnemonic : : PEXTRB , { OPI_MbRv , OPI_V , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 3E0 */ { VXInstructionMnemonic : : PEXTRD , { OPI_Ed , OPI_V , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E1 */ { VXInstructionMnemonic : : PEXTRD , { OPI_Ed , OPI_V , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E2 */ { VXInstructionMnemonic : : PEXTRQ , { OPI_Eq , OPI_V , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 3E3 */ { VXInstructionMnemonic : : PEXTRW , { OPI_MwRd , OPI_V , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E4 */ { VXInstructionMnemonic : : PEXTRW , { OPI_Gd , OPI_N , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E5 */ { VXInstructionMnemonic : : PEXTRW , { OPI_Gd , OPI_U , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E6 */ { VXInstructionMnemonic : : PF2ID , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E7 */ { VXInstructionMnemonic : : PF2IW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3E8 */ { VXInstructionMnemonic : : PFACC , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3E9 */ { VXInstructionMnemonic : : PFADD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3EA */ { VXInstructionMnemonic : : PFCMPEQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3EB */ { VXInstructionMnemonic : : PFCMPGE , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3EC */ { VXInstructionMnemonic : : PFCMPGT , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3ED */ { VXInstructionMnemonic : : PFMAX , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3EE */ { VXInstructionMnemonic : : PFMIN , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3EF */ { VXInstructionMnemonic : : PFMUL , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3F0 */ { VXInstructionMnemonic : : PFNACC , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3F1 */ { VXInstructionMnemonic : : PFPNACC , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3F2 */ { VXInstructionMnemonic : : PFRCP , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3F3 */ { VXInstructionMnemonic : : PFRCPIT1 , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3F4 */ { VXInstructionMnemonic : : PFRCPIT2 , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3F5 */ { VXInstructionMnemonic : : PFRSQIT1 , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3F6 */ { VXInstructionMnemonic : : PFRSQRT , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 3F7 */ { VXInstructionMnemonic : : PFSUB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3F8 */ { VXInstructionMnemonic : : PFSUBR , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3F9 */ { VXInstructionMnemonic : : PHADDD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3FA */ { VXInstructionMnemonic : : PHADDD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3FB */ { VXInstructionMnemonic : : PHADDSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3FC */ { VXInstructionMnemonic : : PHADDSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3FD */ { VXInstructionMnemonic : : PHADDW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3FE */ { VXInstructionMnemonic : : PHADDW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 3FF */ { VXInstructionMnemonic : : PHMINPOSUW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 400 */ { VXInstructionMnemonic : : PHSUBD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 401 */ { VXInstructionMnemonic : : PHSUBD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 402 */ { VXInstructionMnemonic : : PHSUBSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 403 */ { VXInstructionMnemonic : : PHSUBSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 404 */ { VXInstructionMnemonic : : PHSUBW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 405 */ { VXInstructionMnemonic : : PHSUBW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 406 */ { VXInstructionMnemonic : : PI2FD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 407 */ { VXInstructionMnemonic : : PI2FW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 408 */ { VXInstructionMnemonic : : PINSRB , { OPI_V , OPI_MbRd , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 409 */ { VXInstructionMnemonic : : PINSRD , { OPI_V , OPI_Ed , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 40A */ { VXInstructionMnemonic : : PINSRD , { OPI_V , OPI_Ed , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 40B */ { VXInstructionMnemonic : : PINSRQ , { OPI_V , OPI_Eq , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 40C */ { VXInstructionMnemonic : : PINSRW , { OPI_V , OPI_MwRy , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 40D */ { VXInstructionMnemonic : : PINSRW , { OPI_P , OPI_MwRy , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 40E */ { VXInstructionMnemonic : : PMADDUBSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 40F */ { VXInstructionMnemonic : : PMADDUBSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 410 */ { VXInstructionMnemonic : : PMADDWD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 411 */ { VXInstructionMnemonic : : PMADDWD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 412 */ { VXInstructionMnemonic : : PMAXSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 413 */ { VXInstructionMnemonic : : PMAXSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 414 */ { VXInstructionMnemonic : : PMAXSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 415 */ { VXInstructionMnemonic : : PMAXSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 416 */ { VXInstructionMnemonic : : PMAXUB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 417 */ { VXInstructionMnemonic : : PMAXUB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 418 */ { VXInstructionMnemonic : : PMAXUD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 419 */ { VXInstructionMnemonic : : PMAXUW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 41A */ { VXInstructionMnemonic : : PMINSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 41B */ { VXInstructionMnemonic : : PMINSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 41C */ { VXInstructionMnemonic : : PMINSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 41D */ { VXInstructionMnemonic : : PMINSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 41E */ { VXInstructionMnemonic : : PMINUB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 41F */ { VXInstructionMnemonic : : PMINUB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 420 */ { VXInstructionMnemonic : : PMINUD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 421 */ { VXInstructionMnemonic : : PMINUW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 422 */ { VXInstructionMnemonic : : PMOVMSKB , { OPI_Gd , OPI_N , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 423 */ { VXInstructionMnemonic : : PMOVMSKB , { OPI_Gd , OPI_U , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 424 */ { VXInstructionMnemonic : : PMOVSXBD , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 425 */ { VXInstructionMnemonic : : PMOVSXBQ , { OPI_V , OPI_MwU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 426 */ { VXInstructionMnemonic : : PMOVSXBW , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 427 */ { VXInstructionMnemonic : : PMOVSXDQ , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 428 */ { VXInstructionMnemonic : : PMOVSXWD , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 429 */ { VXInstructionMnemonic : : PMOVSXWQ , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 42A */ { VXInstructionMnemonic : : PMOVZXBD , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 42B */ { VXInstructionMnemonic : : PMOVZXBQ , { OPI_V , OPI_MwU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 42C */ { VXInstructionMnemonic : : PMOVZXBW , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 42D */ { VXInstructionMnemonic : : PMOVZXDQ , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 42E */ { VXInstructionMnemonic : : PMOVZXWD , { OPI_V , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 42F */ { VXInstructionMnemonic : : PMOVZXWQ , { OPI_V , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 430 */ { VXInstructionMnemonic : : PMULDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 431 */ { VXInstructionMnemonic : : PMULHRSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 432 */ { VXInstructionMnemonic : : PMULHRSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 433 */ { VXInstructionMnemonic : : PMULHRW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 434 */ { VXInstructionMnemonic : : PMULHUW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 435 */ { VXInstructionMnemonic : : PMULHUW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 436 */ { VXInstructionMnemonic : : PMULHW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 437 */ { VXInstructionMnemonic : : PMULHW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 438 */ { VXInstructionMnemonic : : PMULLD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 439 */ { VXInstructionMnemonic : : PMULLW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 43A */ { VXInstructionMnemonic : : PMULLW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 43B */ { VXInstructionMnemonic : : PMULUDQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 43C */ { VXInstructionMnemonic : : PMULUDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 43D */ { VXInstructionMnemonic : : POP , { OPI_R5v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 43E */ { VXInstructionMnemonic : : POP , { OPI_R4v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 43F */ { VXInstructionMnemonic : : POP , { OPI_R6v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 440 */ { VXInstructionMnemonic : : POP , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 441 */ { VXInstructionMnemonic : : POP , { OPI_R7v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 442 */ { VXInstructionMnemonic : : POP , { OPI_R3v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 443 */ { VXInstructionMnemonic : : POP , { OPI_DS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 | IDF_OPERAND1_WRITE } ,
/* 444 */ { VXInstructionMnemonic : : POP , { OPI_GS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 445 */ { VXInstructionMnemonic : : POP , { OPI_ES , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 | IDF_OPERAND1_WRITE } ,
/* 446 */ { VXInstructionMnemonic : : POP , { OPI_SS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 | IDF_OPERAND1_WRITE } ,
/* 447 */ { VXInstructionMnemonic : : POP , { OPI_R1v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 448 */ { VXInstructionMnemonic : : POP , { OPI_R2v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 449 */ { VXInstructionMnemonic : : POP , { OPI_R0v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 44A */ { VXInstructionMnemonic : : POP , { OPI_FS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 44B */ { VXInstructionMnemonic : : POPA , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_INVALID_64 } ,
/* 44C */ { VXInstructionMnemonic : : POPAD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_INVALID_64 } ,
/* 44D */ { VXInstructionMnemonic : : POPCNT , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 44E */ { VXInstructionMnemonic : : POPFD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 44F */ { VXInstructionMnemonic : : POPFQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 450 */ { VXInstructionMnemonic : : POPFQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 451 */ { VXInstructionMnemonic : : POPFW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 452 */ { VXInstructionMnemonic : : POR , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 453 */ { VXInstructionMnemonic : : POR , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 454 */ { VXInstructionMnemonic : : PREFETCH , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 455 */ { VXInstructionMnemonic : : PREFETCHNTA , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 456 */ { VXInstructionMnemonic : : PREFETCHT0 , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 457 */ { VXInstructionMnemonic : : PREFETCHT1 , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 458 */ { VXInstructionMnemonic : : PREFETCHT2 , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 459 */ { VXInstructionMnemonic : : PSADBW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 45A */ { VXInstructionMnemonic : : PSADBW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 45B */ { VXInstructionMnemonic : : PSHUFB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 45C */ { VXInstructionMnemonic : : PSHUFB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 45D */ { VXInstructionMnemonic : : PSHUFD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 45E */ { VXInstructionMnemonic : : PSHUFHW , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 45F */ { VXInstructionMnemonic : : PSHUFLW , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 460 */ { VXInstructionMnemonic : : PSHUFW , { OPI_P , OPI_Q , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 461 */ { VXInstructionMnemonic : : PSIGNB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 462 */ { VXInstructionMnemonic : : PSIGNB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 463 */ { VXInstructionMnemonic : : PSIGND , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 464 */ { VXInstructionMnemonic : : PSIGND , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 465 */ { VXInstructionMnemonic : : PSIGNW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 466 */ { VXInstructionMnemonic : : PSIGNW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 467 */ { VXInstructionMnemonic : : PSLLD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 468 */ { VXInstructionMnemonic : : PSLLD , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 469 */ { VXInstructionMnemonic : : PSLLD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 46A */ { VXInstructionMnemonic : : PSLLD , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 46B */ { VXInstructionMnemonic : : PSLLDQ , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 46C */ { VXInstructionMnemonic : : PSLLQ , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 46D */ { VXInstructionMnemonic : : PSLLQ , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 46E */ { VXInstructionMnemonic : : PSLLQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 46F */ { VXInstructionMnemonic : : PSLLQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 470 */ { VXInstructionMnemonic : : PSLLW , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 471 */ { VXInstructionMnemonic : : PSLLW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 472 */ { VXInstructionMnemonic : : PSLLW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 473 */ { VXInstructionMnemonic : : PSLLW , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 474 */ { VXInstructionMnemonic : : PSRAD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 475 */ { VXInstructionMnemonic : : PSRAD , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 476 */ { VXInstructionMnemonic : : PSRAD , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 477 */ { VXInstructionMnemonic : : PSRAD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 478 */ { VXInstructionMnemonic : : PSRAW , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 479 */ { VXInstructionMnemonic : : PSRAW , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 47A */ { VXInstructionMnemonic : : PSRAW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 47B */ { VXInstructionMnemonic : : PSRAW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 47C */ { VXInstructionMnemonic : : PSRLD , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 47D */ { VXInstructionMnemonic : : PSRLD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 47E */ { VXInstructionMnemonic : : PSRLD , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 47F */ { VXInstructionMnemonic : : PSRLD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 480 */ { VXInstructionMnemonic : : PSRLDQ , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 481 */ { VXInstructionMnemonic : : PSRLQ , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 482 */ { VXInstructionMnemonic : : PSRLQ , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 483 */ { VXInstructionMnemonic : : PSRLQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 484 */ { VXInstructionMnemonic : : PSRLQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 485 */ { VXInstructionMnemonic : : PSRLW , { OPI_U , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 486 */ { VXInstructionMnemonic : : PSRLW , { OPI_N , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 487 */ { VXInstructionMnemonic : : PSRLW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 488 */ { VXInstructionMnemonic : : PSRLW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 489 */ { VXInstructionMnemonic : : PSUBB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 48A */ { VXInstructionMnemonic : : PSUBB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 48B */ { VXInstructionMnemonic : : PSUBD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 48C */ { VXInstructionMnemonic : : PSUBD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 48D */ { VXInstructionMnemonic : : PSUBQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 48E */ { VXInstructionMnemonic : : PSUBQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 48F */ { VXInstructionMnemonic : : PSUBSB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 490 */ { VXInstructionMnemonic : : PSUBSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 491 */ { VXInstructionMnemonic : : PSUBSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 492 */ { VXInstructionMnemonic : : PSUBSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 493 */ { VXInstructionMnemonic : : PSUBUSB , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 494 */ { VXInstructionMnemonic : : PSUBUSB , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 495 */ { VXInstructionMnemonic : : PSUBUSW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 496 */ { VXInstructionMnemonic : : PSUBUSW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 497 */ { VXInstructionMnemonic : : PSUBW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 498 */ { VXInstructionMnemonic : : PSUBW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 499 */ { VXInstructionMnemonic : : PSWAPD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 49A */ { VXInstructionMnemonic : : PTEST , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 49B */ { VXInstructionMnemonic : : PUNPCKHBW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 49C */ { VXInstructionMnemonic : : PUNPCKHBW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 49D */ { VXInstructionMnemonic : : PUNPCKHDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 49E */ { VXInstructionMnemonic : : PUNPCKHDQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 49F */ { VXInstructionMnemonic : : PUNPCKHQDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A0 */ { VXInstructionMnemonic : : PUNPCKHWD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A1 */ { VXInstructionMnemonic : : PUNPCKHWD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A2 */ { VXInstructionMnemonic : : PUNPCKLBW , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A3 */ { VXInstructionMnemonic : : PUNPCKLBW , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A4 */ { VXInstructionMnemonic : : PUNPCKLDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A5 */ { VXInstructionMnemonic : : PUNPCKLDQ , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A6 */ { VXInstructionMnemonic : : PUNPCKLQDQ , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A7 */ { VXInstructionMnemonic : : PUNPCKLWD , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A8 */ { VXInstructionMnemonic : : PUNPCKLWD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4A9 */ { VXInstructionMnemonic : : PUSH , { OPI_DS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
/* 4AA */ { VXInstructionMnemonic : : PUSH , { OPI_ES , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
/* 4AB */ { VXInstructionMnemonic : : PUSH , { OPI_sIb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_DEFAULT_64 } ,
/* 4AC */ { VXInstructionMnemonic : : PUSH , { OPI_SS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
/* 4AD */ { VXInstructionMnemonic : : PUSH , { OPI_CS , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 } ,
/* 4AE */ { VXInstructionMnemonic : : PUSH , { OPI_R3v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4AF */ { VXInstructionMnemonic : : PUSH , { OPI_R4v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B0 */ { VXInstructionMnemonic : : PUSH , { OPI_R5v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B1 */ { VXInstructionMnemonic : : PUSH , { OPI_R6v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B2 */ { VXInstructionMnemonic : : PUSH , { OPI_R7v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B3 */ { VXInstructionMnemonic : : PUSH , { OPI_R2v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B4 */ { VXInstructionMnemonic : : PUSH , { OPI_R0v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B5 */ { VXInstructionMnemonic : : PUSH , { OPI_FS , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4B6 */ { VXInstructionMnemonic : : PUSH , { OPI_GS , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4B7 */ { VXInstructionMnemonic : : PUSH , { OPI_sIz , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_DEFAULT_64 } ,
/* 4B8 */ { VXInstructionMnemonic : : PUSH , { OPI_Ev , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4B9 */ { VXInstructionMnemonic : : PUSH , { OPI_R1v , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 4BA */ { VXInstructionMnemonic : : PUSHA , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_INVALID_64 } ,
/* 4BB */ { VXInstructionMnemonic : : PUSHAD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_INVALID_64 } ,
/* 4BC */ { VXInstructionMnemonic : : PUSHFD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 4BD */ { VXInstructionMnemonic : : PUSHFQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_DEFAULT_64 } ,
/* 4BE */ { VXInstructionMnemonic : : PUSHFQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_DEFAULT_64 } ,
/* 4BF */ { VXInstructionMnemonic : : PUSHFW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_DEFAULT_64 } ,
/* 4C0 */ { VXInstructionMnemonic : : PUSHFW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX } ,
/* 4C1 */ { VXInstructionMnemonic : : PXOR , { OPI_P , OPI_Q , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C2 */ { VXInstructionMnemonic : : PXOR , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C3 */ { VXInstructionMnemonic : : RCL , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C4 */ { VXInstructionMnemonic : : RCL , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C5 */ { VXInstructionMnemonic : : RCL , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C6 */ { VXInstructionMnemonic : : RCL , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C7 */ { VXInstructionMnemonic : : RCL , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C8 */ { VXInstructionMnemonic : : RCL , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4C9 */ { VXInstructionMnemonic : : RCPPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4CA */ { VXInstructionMnemonic : : RCPSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4CB */ { VXInstructionMnemonic : : RCR , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4CC */ { VXInstructionMnemonic : : RCR , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4CD */ { VXInstructionMnemonic : : RCR , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4CE */ { VXInstructionMnemonic : : RCR , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4CF */ { VXInstructionMnemonic : : RCR , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4D0 */ { VXInstructionMnemonic : : RCR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4D1 */ { VXInstructionMnemonic : : RDMSR , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D2 */ { VXInstructionMnemonic : : RDPMC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D3 */ { VXInstructionMnemonic : : RDRAND , { OPI_R , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4D4 */ { VXInstructionMnemonic : : RDTSC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D5 */ { VXInstructionMnemonic : : RDTSCP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D6 */ { VXInstructionMnemonic : : REP , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D7 */ { VXInstructionMnemonic : : REPNE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D8 */ { VXInstructionMnemonic : : RET , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4D9 */ { VXInstructionMnemonic : : RET , { OPI_Iw , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4DA */ { VXInstructionMnemonic : : RETF , { OPI_Iw , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4DB */ { VXInstructionMnemonic : : RETF , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4DC */ { VXInstructionMnemonic : : ROL , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4DD */ { VXInstructionMnemonic : : ROL , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4DE */ { VXInstructionMnemonic : : ROL , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4DF */ { VXInstructionMnemonic : : ROL , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E0 */ { VXInstructionMnemonic : : ROL , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E1 */ { VXInstructionMnemonic : : ROL , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E2 */ { VXInstructionMnemonic : : ROR , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E3 */ { VXInstructionMnemonic : : ROR , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E4 */ { VXInstructionMnemonic : : ROR , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E5 */ { VXInstructionMnemonic : : ROR , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E6 */ { VXInstructionMnemonic : : ROR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E7 */ { VXInstructionMnemonic : : ROR , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4E8 */ { VXInstructionMnemonic : : ROUNDPD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4E9 */ { VXInstructionMnemonic : : ROUNDPS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4EA */ { VXInstructionMnemonic : : ROUNDSD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4EB */ { VXInstructionMnemonic : : ROUNDSS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4EC */ { VXInstructionMnemonic : : RSM , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4ED */ { VXInstructionMnemonic : : RSQRTPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4EE */ { VXInstructionMnemonic : : RSQRTSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4EF */ { VXInstructionMnemonic : : SAHF , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 4F0 */ { VXInstructionMnemonic : : SALC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_INVALID_64 | IDF_OPERAND1_READWRITE } ,
/* 4F1 */ { VXInstructionMnemonic : : SAR , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4F2 */ { VXInstructionMnemonic : : SAR , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4F3 */ { VXInstructionMnemonic : : SAR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4F4 */ { VXInstructionMnemonic : : SAR , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4F5 */ { VXInstructionMnemonic : : SAR , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4F6 */ { VXInstructionMnemonic : : SAR , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 4F7 */ { VXInstructionMnemonic : : SBB , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4F8 */ { VXInstructionMnemonic : : SBB , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4F9 */ { VXInstructionMnemonic : : SBB , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_WRITE } ,
/* 4FA */ { VXInstructionMnemonic : : SBB , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_WRITE } ,
/* 4FB */ { VXInstructionMnemonic : : SBB , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4FC */ { VXInstructionMnemonic : : SBB , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 | IDF_OPERAND1_WRITE } ,
/* 4FD */ { VXInstructionMnemonic : : SBB , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4FE */ { VXInstructionMnemonic : : SBB , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 4FF */ { VXInstructionMnemonic : : SBB , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 500 */ { VXInstructionMnemonic : : SBB , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 501 */ { VXInstructionMnemonic : : SCASB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 502 */ { VXInstructionMnemonic : : SCASD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 503 */ { VXInstructionMnemonic : : SCASQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 504 */ { VXInstructionMnemonic : : SCASW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 505 */ { VXInstructionMnemonic : : SETA , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 506 */ { VXInstructionMnemonic : : SETAE , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 507 */ { VXInstructionMnemonic : : SETB , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 508 */ { VXInstructionMnemonic : : SETBE , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 509 */ { VXInstructionMnemonic : : SETE , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 50A */ { VXInstructionMnemonic : : SETG , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 50B */ { VXInstructionMnemonic : : SETGE , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 50C */ { VXInstructionMnemonic : : SETL , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 50D */ { VXInstructionMnemonic : : SETLE , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 50E */ { VXInstructionMnemonic : : SETNE , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 50F */ { VXInstructionMnemonic : : SETNO , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 510 */ { VXInstructionMnemonic : : SETNP , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 511 */ { VXInstructionMnemonic : : SETNS , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 512 */ { VXInstructionMnemonic : : SETO , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 513 */ { VXInstructionMnemonic : : SETP , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 514 */ { VXInstructionMnemonic : : SETS , { OPI_Eb , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 515 */ { VXInstructionMnemonic : : SFENCE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 516 */ { VXInstructionMnemonic : : SGDT , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 517 */ { VXInstructionMnemonic : : SHL , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 518 */ { VXInstructionMnemonic : : SHL , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 519 */ { VXInstructionMnemonic : : SHL , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 51A */ { VXInstructionMnemonic : : SHL , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 51B */ { VXInstructionMnemonic : : SHL , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 51C */ { VXInstructionMnemonic : : SHL , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 51D */ { VXInstructionMnemonic : : SHL , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 51E */ { VXInstructionMnemonic : : SHL , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 51F */ { VXInstructionMnemonic : : SHL , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 520 */ { VXInstructionMnemonic : : SHL , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 521 */ { VXInstructionMnemonic : : SHL , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 522 */ { VXInstructionMnemonic : : SHL , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 523 */ { VXInstructionMnemonic : : SHLD , { OPI_Ev , OPI_Gv , OPI_CL , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 524 */ { VXInstructionMnemonic : : SHLD , { OPI_Ev , OPI_Gv , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 525 */ { VXInstructionMnemonic : : SHR , { OPI_Ev , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 526 */ { VXInstructionMnemonic : : SHR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 527 */ { VXInstructionMnemonic : : SHR , { OPI_Eb , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 528 */ { VXInstructionMnemonic : : SHR , { OPI_Ev , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 529 */ { VXInstructionMnemonic : : SHR , { OPI_Eb , OPI_CL , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 52A */ { VXInstructionMnemonic : : SHR , { OPI_Ev , OPI_I1 , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 52B */ { VXInstructionMnemonic : : SHRD , { OPI_Ev , OPI_Gv , OPI_CL , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 52C */ { VXInstructionMnemonic : : SHRD , { OPI_Ev , OPI_Gv , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 52D */ { VXInstructionMnemonic : : SHUFPD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 52E */ { VXInstructionMnemonic : : SHUFPS , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 52F */ { VXInstructionMnemonic : : SIDT , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 530 */ { VXInstructionMnemonic : : SKINIT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 531 */ { VXInstructionMnemonic : : SLDT , { OPI_MwRv , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 532 */ { VXInstructionMnemonic : : SMSW , { OPI_MwRv , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 533 */ { VXInstructionMnemonic : : SMSW , { OPI_MwRv , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 534 */ { VXInstructionMnemonic : : SQRTPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 535 */ { VXInstructionMnemonic : : SQRTPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 536 */ { VXInstructionMnemonic : : SQRTSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 537 */ { VXInstructionMnemonic : : SQRTSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 538 */ { VXInstructionMnemonic : : STC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 539 */ { VXInstructionMnemonic : : STD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 53A */ { VXInstructionMnemonic : : STGI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 53B */ { VXInstructionMnemonic : : STI , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 53C */ { VXInstructionMnemonic : : STMXCSR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 53D */ { VXInstructionMnemonic : : STOSB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 53E */ { VXInstructionMnemonic : : STOSD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 53F */ { VXInstructionMnemonic : : STOSQ , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 540 */ { VXInstructionMnemonic : : STOSW , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REP_PREFIX | IDF_ACCEPTS_SEGMENT_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 541 */ { VXInstructionMnemonic : : STR , { OPI_MwRv , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 542 */ { VXInstructionMnemonic : : SUB , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 543 */ { VXInstructionMnemonic : : SUB , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 544 */ { VXInstructionMnemonic : : SUB , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 545 */ { VXInstructionMnemonic : : SUB , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 546 */ { VXInstructionMnemonic : : SUB , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 | IDF_OPERAND1_READWRITE } ,
/* 547 */ { VXInstructionMnemonic : : SUB , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_READWRITE } ,
/* 548 */ { VXInstructionMnemonic : : SUB , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 549 */ { VXInstructionMnemonic : : SUB , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 54A */ { VXInstructionMnemonic : : SUB , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 54B */ { VXInstructionMnemonic : : SUB , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 54C */ { VXInstructionMnemonic : : SUBPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 54D */ { VXInstructionMnemonic : : SUBPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 54E */ { VXInstructionMnemonic : : SUBSD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 54F */ { VXInstructionMnemonic : : SUBSS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 550 */ { VXInstructionMnemonic : : SWAPGS , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 551 */ { VXInstructionMnemonic : : SYSCALL , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 552 */ { VXInstructionMnemonic : : SYSENTER , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 553 */ { VXInstructionMnemonic : : SYSENTER , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 554 */ { VXInstructionMnemonic : : SYSEXIT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 555 */ { VXInstructionMnemonic : : SYSEXIT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 556 */ { VXInstructionMnemonic : : SYSRET , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 557 */ { VXInstructionMnemonic : : TEST , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 558 */ { VXInstructionMnemonic : : TEST , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 559 */ { VXInstructionMnemonic : : TEST , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 55A */ { VXInstructionMnemonic : : TEST , { OPI_Ev , OPI_Iz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 55B */ { VXInstructionMnemonic : : TEST , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW } ,
/* 55C */ { VXInstructionMnemonic : : TEST , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 55D */ { VXInstructionMnemonic : : TEST , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 55E */ { VXInstructionMnemonic : : TEST , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , 0 } ,
/* 55F */ { VXInstructionMnemonic : : UCOMISD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 560 */ { VXInstructionMnemonic : : UCOMISS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 561 */ { VXInstructionMnemonic : : UD2 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 562 */ { VXInstructionMnemonic : : UNPCKHPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 563 */ { VXInstructionMnemonic : : UNPCKHPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 564 */ { VXInstructionMnemonic : : UNPCKLPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 565 */ { VXInstructionMnemonic : : UNPCKLPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 566 */ { VXInstructionMnemonic : : VADDPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 567 */ { VXInstructionMnemonic : : VADDPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 568 */ { VXInstructionMnemonic : : VADDSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 569 */ { VXInstructionMnemonic : : VADDSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 56A */ { VXInstructionMnemonic : : VADDSUBPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 56B */ { VXInstructionMnemonic : : VADDSUBPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 56C */ { VXInstructionMnemonic : : VAESDEC , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 56D */ { VXInstructionMnemonic : : VAESDECLAST , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 56E */ { VXInstructionMnemonic : : VAESENC , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 56F */ { VXInstructionMnemonic : : VAESENCLAST , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 570 */ { VXInstructionMnemonic : : VAESIMC , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 571 */ { VXInstructionMnemonic : : VAESKEYGENASSIST , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 572 */ { VXInstructionMnemonic : : VANDNPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 573 */ { VXInstructionMnemonic : : VANDNPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 574 */ { VXInstructionMnemonic : : VANDPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 575 */ { VXInstructionMnemonic : : VANDPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 576 */ { VXInstructionMnemonic : : VBLENDPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 577 */ { VXInstructionMnemonic : : VBLENDPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 578 */ { VXInstructionMnemonic : : VBLENDVPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Lx } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 579 */ { VXInstructionMnemonic : : VBLENDVPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Lx } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 57A */ { VXInstructionMnemonic : : VBROADCASTSD , { OPI_Vqq , OPI_Mq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 57B */ { VXInstructionMnemonic : : VBROADCASTSS , { OPI_V , OPI_Md , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 57C */ { VXInstructionMnemonic : : VCMPPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 57D */ { VXInstructionMnemonic : : VCMPPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 57E */ { VXInstructionMnemonic : : VCMPSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 57F */ { VXInstructionMnemonic : : VCMPSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 580 */ { VXInstructionMnemonic : : VCOMISD , { OPI_Vsd , OPI_Wsd , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 581 */ { VXInstructionMnemonic : : VCOMISS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 582 */ { VXInstructionMnemonic : : VCVTDQ2PD , { OPI_Vx , OPI_Wdq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 583 */ { VXInstructionMnemonic : : VCVTDQ2PS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 584 */ { VXInstructionMnemonic : : VCVTPD2DQ , { OPI_Vdq , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 585 */ { VXInstructionMnemonic : : VCVTPD2PS , { OPI_Vdq , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 586 */ { VXInstructionMnemonic : : VCVTPS2DQ , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 587 */ { VXInstructionMnemonic : : VCVTPS2PD , { OPI_Vx , OPI_Wdq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 588 */ { VXInstructionMnemonic : : VCVTSD2SI , { OPI_Gy , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 589 */ { VXInstructionMnemonic : : VCVTSD2SS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 58A */ { VXInstructionMnemonic : : VCVTSI2SD , { OPI_Vx , OPI_Hx , OPI_Ey , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 58B */ { VXInstructionMnemonic : : VCVTSI2SS , { OPI_Vx , OPI_Hx , OPI_Ey , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 58C */ { VXInstructionMnemonic : : VCVTSS2SD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 58D */ { VXInstructionMnemonic : : VCVTSS2SI , { OPI_Gy , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 58E */ { VXInstructionMnemonic : : VCVTTPD2DQ , { OPI_Vdq , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 58F */ { VXInstructionMnemonic : : VCVTTPS2DQ , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 590 */ { VXInstructionMnemonic : : VCVTTSD2SI , { OPI_Gy , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 591 */ { VXInstructionMnemonic : : VCVTTSS2SI , { OPI_Gy , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 592 */ { VXInstructionMnemonic : : VDIVPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 593 */ { VXInstructionMnemonic : : VDIVPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 594 */ { VXInstructionMnemonic : : VDIVSD , { OPI_Vx , OPI_Hx , OPI_MqU , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 595 */ { VXInstructionMnemonic : : VDIVSS , { OPI_Vx , OPI_Hx , OPI_MdU , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 596 */ { VXInstructionMnemonic : : VDPPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 597 */ { VXInstructionMnemonic : : VDPPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 598 */ { VXInstructionMnemonic : : VERR , { OPI_Ew , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 599 */ { VXInstructionMnemonic : : VERW , { OPI_Ew , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 59A */ { VXInstructionMnemonic : : VEXTRACTF128 , { OPI_Wdq , OPI_Vqq , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 59B */ { VXInstructionMnemonic : : VEXTRACTPS , { OPI_MdRy , OPI_Vx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 59C */ { VXInstructionMnemonic : : VHADDPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 59D */ { VXInstructionMnemonic : : VHADDPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 59E */ { VXInstructionMnemonic : : VHSUBPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 59F */ { VXInstructionMnemonic : : VHSUBPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5A0 */ { VXInstructionMnemonic : : VINSERTF128 , { OPI_Vqq , OPI_Hqq , OPI_Wdq , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5A1 */ { VXInstructionMnemonic : : VINSERTPS , { OPI_Vx , OPI_Hx , OPI_Md , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5A2 */ { VXInstructionMnemonic : : VLDDQU , { OPI_Vx , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5A3 */ { VXInstructionMnemonic : : VMASKMOVDQU , { OPI_Vx , OPI_Ux , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 5A4 */ { VXInstructionMnemonic : : VMASKMOVPD , { OPI_M , OPI_H , OPI_V , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5A5 */ { VXInstructionMnemonic : : VMASKMOVPD , { OPI_V , OPI_H , OPI_M , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5A6 */ { VXInstructionMnemonic : : VMASKMOVPS , { OPI_V , OPI_H , OPI_M , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5A7 */ { VXInstructionMnemonic : : VMASKMOVPS , { OPI_M , OPI_H , OPI_V , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5A8 */ { VXInstructionMnemonic : : VMAXPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5A9 */ { VXInstructionMnemonic : : VMAXPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5AA */ { VXInstructionMnemonic : : VMAXSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5AB */ { VXInstructionMnemonic : : VMAXSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5AC */ { VXInstructionMnemonic : : VMCALL , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5AD */ { VXInstructionMnemonic : : VMCLEAR , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 5AE */ { VXInstructionMnemonic : : VMINPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5AF */ { VXInstructionMnemonic : : VMINPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5B0 */ { VXInstructionMnemonic : : VMINSD , { OPI_Vx , OPI_Hx , OPI_MqU , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5B1 */ { VXInstructionMnemonic : : VMINSS , { OPI_Vx , OPI_Hx , OPI_MdU , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5B2 */ { VXInstructionMnemonic : : VMLAUNCH , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5B3 */ { VXInstructionMnemonic : : VMLOAD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5B4 */ { VXInstructionMnemonic : : VMMCALL , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5B5 */ { VXInstructionMnemonic : : VMOVAPD , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5B6 */ { VXInstructionMnemonic : : VMOVAPD , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5B7 */ { VXInstructionMnemonic : : VMOVAPS , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5B8 */ { VXInstructionMnemonic : : VMOVAPS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5B9 */ { VXInstructionMnemonic : : VMOVD , { OPI_Ey , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5BA */ { VXInstructionMnemonic : : VMOVD , { OPI_Vx , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5BB */ { VXInstructionMnemonic : : VMOVD , { OPI_Vx , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5BC */ { VXInstructionMnemonic : : VMOVD , { OPI_Ey , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5BD */ { VXInstructionMnemonic : : VMOVDDUP , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5BE */ { VXInstructionMnemonic : : VMOVDDUP , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5BF */ { VXInstructionMnemonic : : VMOVDQA , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5C0 */ { VXInstructionMnemonic : : VMOVDQA , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5C1 */ { VXInstructionMnemonic : : VMOVDQU , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5C2 */ { VXInstructionMnemonic : : VMOVDQU , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5C3 */ { VXInstructionMnemonic : : VMOVHLPS , { OPI_Vx , OPI_Ux , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5C4 */ { VXInstructionMnemonic : : VMOVHPD , { OPI_Vx , OPI_Hx , OPI_M , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5C5 */ { VXInstructionMnemonic : : VMOVHPD , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5C6 */ { VXInstructionMnemonic : : VMOVHPS , { OPI_Vx , OPI_Hx , OPI_M , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5C7 */ { VXInstructionMnemonic : : VMOVHPS , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5C8 */ { VXInstructionMnemonic : : VMOVLHPS , { OPI_Vx , OPI_Hx , OPI_Ux , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5C9 */ { VXInstructionMnemonic : : VMOVLPD , { OPI_Vx , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5CA */ { VXInstructionMnemonic : : VMOVLPD , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5CB */ { VXInstructionMnemonic : : VMOVLPS , { OPI_Vx , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5CC */ { VXInstructionMnemonic : : VMOVLPS , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5CD */ { VXInstructionMnemonic : : VMOVMSKPD , { OPI_Gd , OPI_Ux , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5CE */ { VXInstructionMnemonic : : VMOVMSKPS , { OPI_Gd , OPI_Ux , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5CF */ { VXInstructionMnemonic : : VMOVNTDQ , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5D0 */ { VXInstructionMnemonic : : VMOVNTDQA , { OPI_Vx , OPI_M , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5D1 */ { VXInstructionMnemonic : : VMOVNTPD , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5D2 */ { VXInstructionMnemonic : : VMOVNTPS , { OPI_M , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5D3 */ { VXInstructionMnemonic : : VMOVQ , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5D4 */ { VXInstructionMnemonic : : VMOVQ , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5D5 */ { VXInstructionMnemonic : : VMOVQ , { OPI_Vx , OPI_Eq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5D6 */ { VXInstructionMnemonic : : VMOVQ , { OPI_Eq , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5D7 */ { VXInstructionMnemonic : : VMOVSD , { OPI_U , OPI_H , OPI_V , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5D8 */ { VXInstructionMnemonic : : VMOVSD , { OPI_Mq , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5D9 */ { VXInstructionMnemonic : : VMOVSD , { OPI_V , OPI_H , OPI_U , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5DA */ { VXInstructionMnemonic : : VMOVSD , { OPI_V , OPI_Mq , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5DB */ { VXInstructionMnemonic : : VMOVSHDUP , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5DC */ { VXInstructionMnemonic : : VMOVSHDUP , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5DD */ { VXInstructionMnemonic : : VMOVSLDUP , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5DE */ { VXInstructionMnemonic : : VMOVSLDUP , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5DF */ { VXInstructionMnemonic : : VMOVSS , { OPI_V , OPI_H , OPI_U , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5E0 */ { VXInstructionMnemonic : : VMOVSS , { OPI_Md , OPI_V , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5E1 */ { VXInstructionMnemonic : : VMOVSS , { OPI_U , OPI_H , OPI_V , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5E2 */ { VXInstructionMnemonic : : VMOVSS , { OPI_V , OPI_Md , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 5E3 */ { VXInstructionMnemonic : : VMOVUPD , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5E4 */ { VXInstructionMnemonic : : VMOVUPD , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5E5 */ { VXInstructionMnemonic : : VMOVUPS , { OPI_Wx , OPI_Vx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5E6 */ { VXInstructionMnemonic : : VMOVUPS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5E7 */ { VXInstructionMnemonic : : VMPSADBW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5E8 */ { VXInstructionMnemonic : : VMPTRLD , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 5E9 */ { VXInstructionMnemonic : : VMPTRST , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 5EA */ { VXInstructionMnemonic : : VMREAD , { OPI_Ey , OPI_Gy , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 5EB */ { VXInstructionMnemonic : : VMRESUME , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5EC */ { VXInstructionMnemonic : : VMRUN , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5ED */ { VXInstructionMnemonic : : VMSAVE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5EE */ { VXInstructionMnemonic : : VMULPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5EF */ { VXInstructionMnemonic : : VMULPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5F0 */ { VXInstructionMnemonic : : VMULSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5F1 */ { VXInstructionMnemonic : : VMULSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 5F2 */ { VXInstructionMnemonic : : VMWRITE , { OPI_Gy , OPI_Ey , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 } ,
/* 5F3 */ { VXInstructionMnemonic : : VMXOFF , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 5F4 */ { VXInstructionMnemonic : : VMXON , { OPI_Mq , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 5F5 */ { VXInstructionMnemonic : : VORPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5F6 */ { VXInstructionMnemonic : : VORPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL } ,
/* 5F7 */ { VXInstructionMnemonic : : VPABSB , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5F8 */ { VXInstructionMnemonic : : VPABSD , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5F9 */ { VXInstructionMnemonic : : VPABSW , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 5FA */ { VXInstructionMnemonic : : VPACKSSDW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5FB */ { VXInstructionMnemonic : : VPACKSSWB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5FC */ { VXInstructionMnemonic : : VPACKUSDW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5FD */ { VXInstructionMnemonic : : VPACKUSWB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5FE */ { VXInstructionMnemonic : : VPADDB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 5FF */ { VXInstructionMnemonic : : VPADDD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 600 */ { VXInstructionMnemonic : : VPADDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 601 */ { VXInstructionMnemonic : : VPADDSB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 602 */ { VXInstructionMnemonic : : VPADDSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 603 */ { VXInstructionMnemonic : : VPADDUSB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 604 */ { VXInstructionMnemonic : : VPADDUSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 605 */ { VXInstructionMnemonic : : VPADDW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 606 */ { VXInstructionMnemonic : : VPALIGNR , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 607 */ { VXInstructionMnemonic : : VPAND , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 608 */ { VXInstructionMnemonic : : VPANDN , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 609 */ { VXInstructionMnemonic : : VPAVGB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 60A */ { VXInstructionMnemonic : : VPAVGW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 60B */ { VXInstructionMnemonic : : VPBLENDVB , { OPI_V , OPI_H , OPI_W , OPI_L } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 60C */ { VXInstructionMnemonic : : VPBLENDW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 60D */ { VXInstructionMnemonic : : VPCLMULQDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 60E */ { VXInstructionMnemonic : : VPCMPEQB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 60F */ { VXInstructionMnemonic : : VPCMPEQD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 610 */ { VXInstructionMnemonic : : VPCMPEQQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 611 */ { VXInstructionMnemonic : : VPCMPEQW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 612 */ { VXInstructionMnemonic : : VPCMPESTRI , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 613 */ { VXInstructionMnemonic : : VPCMPESTRM , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 614 */ { VXInstructionMnemonic : : VPCMPGTB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 615 */ { VXInstructionMnemonic : : VPCMPGTD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 616 */ { VXInstructionMnemonic : : VPCMPGTQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 617 */ { VXInstructionMnemonic : : VPCMPGTW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 618 */ { VXInstructionMnemonic : : VPCMPISTRI , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 619 */ { VXInstructionMnemonic : : VPCMPISTRM , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 61A */ { VXInstructionMnemonic : : VPERM2F128 , { OPI_Vqq , OPI_Hqq , OPI_Wqq , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 61B */ { VXInstructionMnemonic : : VPERMILPD , { OPI_V , OPI_W , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 61C */ { VXInstructionMnemonic : : VPERMILPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 61D */ { VXInstructionMnemonic : : VPERMILPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 61E */ { VXInstructionMnemonic : : VPERMILPS , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 61F */ { VXInstructionMnemonic : : VPEXTRB , { OPI_MbRv , OPI_Vx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 620 */ { VXInstructionMnemonic : : VPEXTRD , { OPI_Ed , OPI_Vx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 621 */ { VXInstructionMnemonic : : VPEXTRD , { OPI_Ed , OPI_Vx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 622 */ { VXInstructionMnemonic : : VPEXTRQ , { OPI_Eq , OPI_Vx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 623 */ { VXInstructionMnemonic : : VPEXTRW , { OPI_Gd , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 624 */ { VXInstructionMnemonic : : VPEXTRW , { OPI_MwRd , OPI_Vx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 625 */ { VXInstructionMnemonic : : VPHADDD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 626 */ { VXInstructionMnemonic : : VPHADDSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 627 */ { VXInstructionMnemonic : : VPHADDW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 628 */ { VXInstructionMnemonic : : VPHMINPOSUW , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 629 */ { VXInstructionMnemonic : : VPHSUBD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 62A */ { VXInstructionMnemonic : : VPHSUBSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 62B */ { VXInstructionMnemonic : : VPHSUBW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 62C */ { VXInstructionMnemonic : : VPINSRB , { OPI_V , OPI_H , OPI_MbRd , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 62D */ { VXInstructionMnemonic : : VPINSRD , { OPI_V , OPI_H , OPI_Ed , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 62E */ { VXInstructionMnemonic : : VPINSRD , { OPI_V , OPI_H , OPI_Ed , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 62F */ { VXInstructionMnemonic : : VPINSRQ , { OPI_V , OPI_H , OPI_Eq , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 630 */ { VXInstructionMnemonic : : VPINSRW , { OPI_Vx , OPI_MwRy , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_DEFAULT_64 | IDF_OPERAND1_WRITE } ,
/* 631 */ { VXInstructionMnemonic : : VPMADDUBSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 632 */ { VXInstructionMnemonic : : VPMADDWD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 633 */ { VXInstructionMnemonic : : VPMAXSB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 634 */ { VXInstructionMnemonic : : VPMAXSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 635 */ { VXInstructionMnemonic : : VPMAXSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 636 */ { VXInstructionMnemonic : : VPMAXUB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 637 */ { VXInstructionMnemonic : : VPMAXUD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 638 */ { VXInstructionMnemonic : : VPMAXUW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 639 */ { VXInstructionMnemonic : : VPMINSB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 63A */ { VXInstructionMnemonic : : VPMINSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 63B */ { VXInstructionMnemonic : : VPMINSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 63C */ { VXInstructionMnemonic : : VPMINUB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 63D */ { VXInstructionMnemonic : : VPMINUD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 63E */ { VXInstructionMnemonic : : VPMINUW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 63F */ { VXInstructionMnemonic : : VPMOVMSKB , { OPI_Gd , OPI_Ux , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 640 */ { VXInstructionMnemonic : : VPMOVSXBD , { OPI_Vx , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 641 */ { VXInstructionMnemonic : : VPMOVSXBQ , { OPI_Vx , OPI_MwU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 642 */ { VXInstructionMnemonic : : VPMOVSXBW , { OPI_Vx , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 643 */ { VXInstructionMnemonic : : VPMOVSXWD , { OPI_Vx , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 644 */ { VXInstructionMnemonic : : VPMOVSXWQ , { OPI_Vx , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 645 */ { VXInstructionMnemonic : : VPMOVZXBD , { OPI_Vx , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 646 */ { VXInstructionMnemonic : : VPMOVZXBQ , { OPI_Vx , OPI_MwU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 647 */ { VXInstructionMnemonic : : VPMOVZXBW , { OPI_Vx , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 648 */ { VXInstructionMnemonic : : VPMOVZXDQ , { OPI_Vx , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 649 */ { VXInstructionMnemonic : : VPMOVZXWD , { OPI_Vx , OPI_MqU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 64A */ { VXInstructionMnemonic : : VPMOVZXWQ , { OPI_Vx , OPI_MdU , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 64B */ { VXInstructionMnemonic : : VPMULDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 64C */ { VXInstructionMnemonic : : VPMULHRSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 64D */ { VXInstructionMnemonic : : VPMULHUW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 64E */ { VXInstructionMnemonic : : VPMULHW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 64F */ { VXInstructionMnemonic : : VPMULLD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 650 */ { VXInstructionMnemonic : : VPMULLW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 651 */ { VXInstructionMnemonic : : VPOR , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 652 */ { VXInstructionMnemonic : : VPSADBW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 653 */ { VXInstructionMnemonic : : VPSHUFB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 654 */ { VXInstructionMnemonic : : VPSHUFD , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 655 */ { VXInstructionMnemonic : : VPSHUFHW , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 656 */ { VXInstructionMnemonic : : VPSHUFLW , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 657 */ { VXInstructionMnemonic : : VPSIGNB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 658 */ { VXInstructionMnemonic : : VPSIGND , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 659 */ { VXInstructionMnemonic : : VPSIGNW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 65A */ { VXInstructionMnemonic : : VPSLLD , { OPI_H , OPI_V , OPI_W , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 65B */ { VXInstructionMnemonic : : VPSLLD , { OPI_V , OPI_H , OPI_W , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 65C */ { VXInstructionMnemonic : : VPSLLDQ , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 65D */ { VXInstructionMnemonic : : VPSLLQ , { OPI_V , OPI_H , OPI_W , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 65E */ { VXInstructionMnemonic : : VPSLLQ , { OPI_H , OPI_V , OPI_W , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 65F */ { VXInstructionMnemonic : : VPSLLW , { OPI_V , OPI_H , OPI_W , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 660 */ { VXInstructionMnemonic : : VPSLLW , { OPI_H , OPI_V , OPI_W , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 661 */ { VXInstructionMnemonic : : VPSRAD , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 662 */ { VXInstructionMnemonic : : VPSRAD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 663 */ { VXInstructionMnemonic : : VPSRAW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 664 */ { VXInstructionMnemonic : : VPSRAW , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 665 */ { VXInstructionMnemonic : : VPSRLD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 666 */ { VXInstructionMnemonic : : VPSRLD , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 667 */ { VXInstructionMnemonic : : VPSRLDQ , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 668 */ { VXInstructionMnemonic : : VPSRLQ , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 669 */ { VXInstructionMnemonic : : VPSRLQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 66A */ { VXInstructionMnemonic : : VPSRLW , { OPI_Hx , OPI_Ux , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 66B */ { VXInstructionMnemonic : : VPSRLW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 66C */ { VXInstructionMnemonic : : VPSUBB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 66D */ { VXInstructionMnemonic : : VPSUBD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 66E */ { VXInstructionMnemonic : : VPSUBQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 66F */ { VXInstructionMnemonic : : VPSUBSB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 670 */ { VXInstructionMnemonic : : VPSUBSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 671 */ { VXInstructionMnemonic : : VPSUBUSB , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 672 */ { VXInstructionMnemonic : : VPSUBUSW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 673 */ { VXInstructionMnemonic : : VPSUBW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 674 */ { VXInstructionMnemonic : : VPTEST , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL } ,
/* 675 */ { VXInstructionMnemonic : : VPUNPCKHBW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 676 */ { VXInstructionMnemonic : : VPUNPCKHDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 677 */ { VXInstructionMnemonic : : VPUNPCKHQDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 678 */ { VXInstructionMnemonic : : VPUNPCKHWD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 679 */ { VXInstructionMnemonic : : VPUNPCKLBW , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 67A */ { VXInstructionMnemonic : : VPUNPCKLDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 67B */ { VXInstructionMnemonic : : VPUNPCKLQDQ , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 67C */ { VXInstructionMnemonic : : VPUNPCKLWD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 67D */ { VXInstructionMnemonic : : VPXOR , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 67E */ { VXInstructionMnemonic : : VRCPPS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 67F */ { VXInstructionMnemonic : : VRCPSS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 680 */ { VXInstructionMnemonic : : VROUNDPD , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 681 */ { VXInstructionMnemonic : : VROUNDPS , { OPI_Vx , OPI_Wx , OPI_Ib , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 682 */ { VXInstructionMnemonic : : VROUNDSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 683 */ { VXInstructionMnemonic : : VROUNDSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 684 */ { VXInstructionMnemonic : : VRSQRTPS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 685 */ { VXInstructionMnemonic : : VRSQRTSS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 686 */ { VXInstructionMnemonic : : VSHUFPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 687 */ { VXInstructionMnemonic : : VSHUFPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_Ib } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 688 */ { VXInstructionMnemonic : : VSQRTPD , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 689 */ { VXInstructionMnemonic : : VSQRTPS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_WRITE } ,
/* 68A */ { VXInstructionMnemonic : : VSQRTSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 68B */ { VXInstructionMnemonic : : VSQRTSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 68C */ { VXInstructionMnemonic : : VSTMXCSR , { OPI_Md , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_WRITE } ,
/* 68D */ { VXInstructionMnemonic : : VSUBPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 68E */ { VXInstructionMnemonic : : VSUBPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 68F */ { VXInstructionMnemonic : : VSUBSD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 690 */ { VXInstructionMnemonic : : VSUBSS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 691 */ { VXInstructionMnemonic : : VTESTPD , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL } ,
/* 692 */ { VXInstructionMnemonic : : VTESTPS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL } ,
/* 693 */ { VXInstructionMnemonic : : VUCOMISD , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 694 */ { VXInstructionMnemonic : : VUCOMISS , { OPI_Vx , OPI_Wx , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 695 */ { VXInstructionMnemonic : : VUNPCKHPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 696 */ { VXInstructionMnemonic : : VUNPCKHPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 697 */ { VXInstructionMnemonic : : VUNPCKLPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 698 */ { VXInstructionMnemonic : : VUNPCKLPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 699 */ { VXInstructionMnemonic : : VXORPD , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_ACCEPTS_VEXL | IDF_OPERAND1_READWRITE } ,
/* 69A */ { VXInstructionMnemonic : : VXORPS , { OPI_Vx , OPI_Hx , OPI_Wx , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 69B */ { VXInstructionMnemonic : : VZEROALL , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 69C */ { VXInstructionMnemonic : : VZEROUPPER , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 69D */ { VXInstructionMnemonic : : WAIT , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 69E */ { VXInstructionMnemonic : : WBINVD , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 69F */ { VXInstructionMnemonic : : WRMSR , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6A0 */ { VXInstructionMnemonic : : XADD , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_WRITE } ,
/* 6A1 */ { VXInstructionMnemonic : : XADD , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_WRITE } ,
/* 6A2 */ { VXInstructionMnemonic : : XCHG , { OPI_R4v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A3 */ { VXInstructionMnemonic : : XCHG , { OPI_R3v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A4 */ { VXInstructionMnemonic : : XCHG , { OPI_R5v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A5 */ { VXInstructionMnemonic : : XCHG , { OPI_R7v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A6 */ { VXInstructionMnemonic : : XCHG , { OPI_R6v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A7 */ { VXInstructionMnemonic : : XCHG , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A8 */ { VXInstructionMnemonic : : XCHG , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6A9 */ { VXInstructionMnemonic : : XCHG , { OPI_R0v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6AA */ { VXInstructionMnemonic : : XCHG , { OPI_R2v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6AB */ { VXInstructionMnemonic : : XCHG , { OPI_R1v , OPI_rAX , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE | IDF_OPERAND2_READWRITE } ,
/* 6AC */ { VXInstructionMnemonic : : XCRYPTCBC , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6AD */ { VXInstructionMnemonic : : XCRYPTCFB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6AE */ { VXInstructionMnemonic : : XCRYPTCTR , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6AF */ { VXInstructionMnemonic : : XCRYPTECB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6B0 */ { VXInstructionMnemonic : : XCRYPTOFB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6B1 */ { VXInstructionMnemonic : : XGETBV , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6B2 */ { VXInstructionMnemonic : : XLATB , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_REXW | IDF_ACCEPTS_SEGMENT_PREFIX } ,
/* 6B3 */ { VXInstructionMnemonic : : XOR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_INVALID_64 | IDF_OPERAND1_READWRITE } ,
/* 6B4 */ { VXInstructionMnemonic : : XOR , { OPI_Ev , OPI_sIb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6B5 */ { VXInstructionMnemonic : : XOR , { OPI_Ev , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6B6 */ { VXInstructionMnemonic : : XOR , { OPI_Gb , OPI_Eb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6B7 */ { VXInstructionMnemonic : : XOR , { OPI_Gv , OPI_Ev , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6B8 */ { VXInstructionMnemonic : : XOR , { OPI_Eb , OPI_Gb , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6B9 */ { VXInstructionMnemonic : : XOR , { OPI_Ev , OPI_Gv , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6BA */ { VXInstructionMnemonic : : XOR , { OPI_AL , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_OPERAND1_READWRITE } ,
/* 6BB */ { VXInstructionMnemonic : : XOR , { OPI_rAX , OPI_sIz , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_OPERAND_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_OPERAND1_READWRITE } ,
/* 6BC */ { VXInstructionMnemonic : : XOR , { OPI_Eb , OPI_Ib , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6BD */ { VXInstructionMnemonic : : XORPD , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6BE */ { VXInstructionMnemonic : : XORPS , { OPI_V , OPI_W , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB | IDF_OPERAND1_READWRITE } ,
/* 6BF */ { VXInstructionMnemonic : : XRSTOR , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 6C0 */ { VXInstructionMnemonic : : XSAVE , { OPI_M , OPI_NONE , OPI_NONE , OPI_NONE } , IDF_ACCEPTS_ADDRESS_SIZE_PREFIX | IDF_ACCEPTS_REXW | IDF_ACCEPTS_REXR | IDF_ACCEPTS_REXX | IDF_ACCEPTS_REXB } ,
/* 6C1 */ { VXInstructionMnemonic : : XSETBV , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6C2 */ { VXInstructionMnemonic : : XSHA1 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6C3 */ { VXInstructionMnemonic : : XSHA256 , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
/* 6C4 */ { VXInstructionMnemonic : : XSTORE , { OPI_NONE , OPI_NONE , OPI_NONE , OPI_NONE } , 0 } ,
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} ;
# undef OPI_NONE
# undef OPI_AL
# undef OPI_AX
# undef OPI_Av
# undef OPI_C
# undef OPI_CL
# undef OPI_CS
# undef OPI_CX
# undef OPI_D
# undef OPI_DL
# undef OPI_DS
# undef OPI_DX
# undef OPI_E
# undef OPI_ES
# undef OPI_Eb
# undef OPI_Ed
# undef OPI_Eq
# undef OPI_Ev
# undef OPI_Ew
# undef OPI_Ey
# undef OPI_Ez
# undef OPI_FS
# undef OPI_Fv
# undef OPI_G
# undef OPI_GS
# undef OPI_Gb
# undef OPI_Gd
# undef OPI_Gq
# undef OPI_Gv
# undef OPI_Gw
# undef OPI_Gy
# undef OPI_Gz
# undef OPI_H
# undef OPI_Hqq
# undef OPI_Hx
# undef OPI_I1
# undef OPI_Ib
# undef OPI_Iv
# undef OPI_Iw
# undef OPI_Iz
# undef OPI_Jb
# undef OPI_Jv
# undef OPI_Jz
# undef OPI_L
# undef OPI_Lx
# undef OPI_M
# undef OPI_Mb
# undef OPI_MbRd
# undef OPI_MbRv
# undef OPI_Md
# undef OPI_MdRy
# undef OPI_MdU
# undef OPI_Mdq
# undef OPI_Mo
# undef OPI_Mq
# undef OPI_MqU
# undef OPI_Ms
# undef OPI_Mt
# undef OPI_Mv
# undef OPI_Mw
# undef OPI_MwRd
# undef OPI_MwRv
# undef OPI_MwRy
# undef OPI_MwU
# undef OPI_N
# undef OPI_Ob
# undef OPI_Ov
# undef OPI_Ow
# undef OPI_P
# undef OPI_Q
# undef OPI_R
# undef OPI_R0b
# undef OPI_R0v
# undef OPI_R0w
# undef OPI_R0y
# undef OPI_R0z
# undef OPI_R1b
# undef OPI_R1v
# undef OPI_R1w
# undef OPI_R1y
# undef OPI_R1z
# undef OPI_R2b
# undef OPI_R2v
# undef OPI_R2w
# undef OPI_R2y
# undef OPI_R2z
# undef OPI_R3b
# undef OPI_R3v
# undef OPI_R3w
# undef OPI_R3y
# undef OPI_R3z
# undef OPI_R4b
# undef OPI_R4v
# undef OPI_R4w
# undef OPI_R4y
# undef OPI_R4z
# undef OPI_R5b
# undef OPI_R5v
# undef OPI_R5w
# undef OPI_R5y
# undef OPI_R5z
# undef OPI_R6b
# undef OPI_R6v
# undef OPI_R6w
# undef OPI_R6y
# undef OPI_R6z
# undef OPI_R7b
# undef OPI_R7v
# undef OPI_R7w
# undef OPI_R7y
# undef OPI_R7z
# undef OPI_S
# undef OPI_SS
# undef OPI_ST0
# undef OPI_ST1
# undef OPI_ST2
# undef OPI_ST3
# undef OPI_ST4
# undef OPI_ST5
# undef OPI_ST6
# undef OPI_ST7
# undef OPI_U
# undef OPI_Ux
# undef OPI_V
# undef OPI_Vdq
# undef OPI_Vqq
# undef OPI_Vsd
# undef OPI_Vx
# undef OPI_W
# undef OPI_Wdq
# undef OPI_Wqq
# undef OPI_Wsd
# undef OPI_Wx
# undef OPI_eAX
# undef OPI_eCX
# undef OPI_eDX
# undef OPI_rAX
# undef OPI_rCX
2014-10-27 21:10:22 +08:00
# undef OPI_rDX
# undef OPI_sIb
# undef OPI_sIz
2014-10-25 05:11:16 +08:00
const char * instrMnemonicStrings [ ] =
{
/* 000 */ " invalid " ,
/* 001 */ " aaa " ,
/* 002 */ " aad " ,
/* 003 */ " aam " ,
/* 004 */ " aas " ,
/* 005 */ " adc " ,
/* 006 */ " add " ,
/* 007 */ " addpd " ,
/* 008 */ " addps " ,
/* 009 */ " addsd " ,
/* 00A */ " addss " ,
/* 00B */ " addsubpd " ,
/* 00C */ " addsubps " ,
/* 00D */ " aesdec " ,
/* 00E */ " aesdeclast " ,
/* 00F */ " aesenc " ,
/* 010 */ " aesenclast " ,
/* 011 */ " aesimc " ,
/* 012 */ " aeskeygenassist " ,
/* 013 */ " and " ,
/* 014 */ " andnpd " ,
/* 015 */ " andnps " ,
/* 016 */ " andpd " ,
/* 017 */ " andps " ,
/* 018 */ " arpl " ,
/* 019 */ " blendpd " ,
/* 01A */ " blendps " ,
/* 01B */ " blendvpd " ,
/* 01C */ " blendvps " ,
/* 01D */ " bound " ,
/* 01E */ " bsf " ,
/* 01F */ " bsr " ,
/* 020 */ " bswap " ,
/* 021 */ " bt " ,
/* 022 */ " btc " ,
/* 023 */ " btr " ,
/* 024 */ " bts " ,
/* 025 */ " call " ,
/* 026 */ " cbw " ,
/* 027 */ " cdq " ,
/* 028 */ " cdqe " ,
/* 029 */ " clc " ,
/* 02A */ " cld " ,
/* 02B */ " clflush " ,
/* 02C */ " clgi " ,
/* 02D */ " cli " ,
/* 02E */ " clts " ,
/* 02F */ " cmc " ,
/* 030 */ " cmova " ,
/* 031 */ " cmovae " ,
/* 032 */ " cmovb " ,
/* 033 */ " cmovbe " ,
2014-10-27 21:10:22 +08:00
/* 034 */ " cmove " ,
/* 035 */ " cmovg " ,
/* 036 */ " cmovge " ,
/* 037 */ " cmovl " ,
/* 038 */ " cmovle " ,
/* 039 */ " cmovne " ,
/* 03A */ " cmovno " ,
/* 03B */ " cmovnp " ,
/* 03C */ " cmovns " ,
/* 03D */ " cmovo " ,
/* 03E */ " cmovp " ,
/* 03F */ " cmovs " ,
2014-10-25 05:11:16 +08:00
/* 040 */ " cmp " ,
/* 041 */ " cmppd " ,
/* 042 */ " cmpps " ,
/* 043 */ " cmpsb " ,
/* 044 */ " cmpsd " ,
/* 045 */ " cmpsq " ,
/* 046 */ " cmpss " ,
/* 047 */ " cmpsw " ,
/* 048 */ " cmpxchg " ,
/* 049 */ " cmpxchg16b " ,
/* 04A */ " cmpxchg8b " ,
/* 04B */ " comisd " ,
/* 04C */ " comiss " ,
/* 04D */ " cpuid " ,
/* 04E */ " cqo " ,
/* 04F */ " crc32 " ,
/* 050 */ " cvtdq2pd " ,
/* 051 */ " cvtdq2ps " ,
/* 052 */ " cvtpd2dq " ,
/* 053 */ " cvtpd2pi " ,
/* 054 */ " cvtpd2ps " ,
/* 055 */ " cvtpi2pd " ,
/* 056 */ " cvtpi2ps " ,
/* 057 */ " cvtps2dq " ,
/* 058 */ " cvtps2pd " ,
/* 059 */ " cvtps2pi " ,
/* 05A */ " cvtsd2si " ,
/* 05B */ " cvtsd2ss " ,
/* 05C */ " cvtsi2sd " ,
/* 05D */ " cvtsi2ss " ,
/* 05E */ " cvtss2sd " ,
/* 05F */ " cvtss2si " ,
/* 060 */ " cvttpd2dq " ,
/* 061 */ " cvttpd2pi " ,
/* 062 */ " cvttps2dq " ,
/* 063 */ " cvttps2pi " ,
/* 064 */ " cvttsd2si " ,
/* 065 */ " cvttss2si " ,
/* 066 */ " cwd " ,
/* 067 */ " cwde " ,
/* 068 */ " daa " ,
/* 069 */ " das " ,
/* 06A */ " dec " ,
/* 06B */ " div " ,
/* 06C */ " divpd " ,
/* 06D */ " divps " ,
/* 06E */ " divsd " ,
/* 06F */ " divss " ,
/* 070 */ " dppd " ,
/* 071 */ " dpps " ,
/* 072 */ " emms " ,
/* 073 */ " enter " ,
/* 074 */ " extractps " ,
/* 075 */ " f2xm1 " ,
/* 076 */ " fabs " ,
/* 077 */ " fadd " ,
/* 078 */ " faddp " ,
/* 079 */ " fbld " ,
/* 07A */ " fbstp " ,
/* 07B */ " fchs " ,
/* 07C */ " fclex " ,
/* 07D */ " fcmovb " ,
/* 07E */ " fcmovbe " ,
/* 07F */ " fcmove " ,
/* 080 */ " fcmovnb " ,
/* 081 */ " fcmovnbe " ,
/* 082 */ " fcmovne " ,
/* 083 */ " fcmovnu " ,
/* 084 */ " fcmovu " ,
/* 085 */ " fcom " ,
/* 086 */ " fcom2 " ,
/* 087 */ " fcomi " ,
/* 088 */ " fcomip " ,
/* 089 */ " fcomp " ,
/* 08A */ " fcomp3 " ,
/* 08B */ " fcomp5 " ,
/* 08C */ " fcompp " ,
/* 08D */ " fcos " ,
/* 08E */ " fdecstp " ,
/* 08F */ " fdiv " ,
/* 090 */ " fdivp " ,
/* 091 */ " fdivr " ,
/* 092 */ " fdivrp " ,
/* 093 */ " femms " ,
/* 094 */ " ffree " ,
/* 095 */ " ffreep " ,
/* 096 */ " fiadd " ,
/* 097 */ " ficom " ,
/* 098 */ " ficomp " ,
/* 099 */ " fidiv " ,
/* 09A */ " fidivr " ,
/* 09B */ " fild " ,
/* 09C */ " fimul " ,
/* 09D */ " fincstp " ,
/* 09E */ " fist " ,
/* 09F */ " fistp " ,
/* 0A0 */ " fisttp " ,
/* 0A1 */ " fisub " ,
/* 0A2 */ " fisubr " ,
/* 0A3 */ " fld " ,
/* 0A4 */ " fld1 " ,
/* 0A5 */ " fldcw " ,
/* 0A6 */ " fldenv " ,
/* 0A7 */ " fldl2e " ,
/* 0A8 */ " fldl2t " ,
/* 0A9 */ " fldlg2 " ,
/* 0AA */ " fldln2 " ,
/* 0AB */ " fldpi " ,
/* 0AC */ " fldz " ,
/* 0AD */ " fmul " ,
/* 0AE */ " fmulp " ,
2014-10-27 21:10:22 +08:00
/* 0AF */ " fndisi " ,
/* 0B0 */ " fneni " ,
/* 0B1 */ " fninit " ,
/* 0B2 */ " fnop " ,
/* 0B3 */ " fnsave " ,
/* 0B4 */ " fnsetpm " ,
/* 0B5 */ " fnstcw " ,
/* 0B6 */ " fnstenv " ,
/* 0B7 */ " fnstsw " ,
/* 0B8 */ " fpatan " ,
/* 0B9 */ " fprem " ,
/* 0BA */ " fprem1 " ,
/* 0BB */ " fptan " ,
/* 0BC */ " frndint " ,
/* 0BD */ " frstor " ,
/* 0BE */ " frstpm " ,
/* 0BF */ " fscale " ,
/* 0C0 */ " fsin " ,
/* 0C1 */ " fsincos " ,
/* 0C2 */ " fsqrt " ,
/* 0C3 */ " fst " ,
/* 0C4 */ " fstp " ,
/* 0C5 */ " fstp1 " ,
/* 0C6 */ " fstp8 " ,
/* 0C7 */ " fstp9 " ,
/* 0C8 */ " fsub " ,
/* 0C9 */ " fsubp " ,
/* 0CA */ " fsubr " ,
/* 0CB */ " fsubrp " ,
/* 0CC */ " ftst " ,
/* 0CD */ " fucom " ,
/* 0CE */ " fucomi " ,
/* 0CF */ " fucomip " ,
/* 0D0 */ " fucomp " ,
/* 0D1 */ " fucompp " ,
/* 0D2 */ " fxam " ,
/* 0D3 */ " fxch " ,
/* 0D4 */ " fxch4 " ,
/* 0D5 */ " fxch7 " ,
/* 0D6 */ " fxrstor " ,
/* 0D7 */ " fxsave " ,
/* 0D8 */ " fxtract " ,
/* 0D9 */ " fyl2x " ,
/* 0DA */ " fyl2xp1 " ,
/* 0DB */ " getsec " ,
/* 0DC */ " haddpd " ,
/* 0DD */ " haddps " ,
/* 0DE */ " hlt " ,
/* 0DF */ " hsubpd " ,
/* 0E0 */ " hsubps " ,
/* 0E1 */ " idiv " ,
/* 0E2 */ " imul " ,
/* 0E3 */ " in " ,
/* 0E4 */ " inc " ,
/* 0E5 */ " insb " ,
/* 0E6 */ " insd " ,
/* 0E7 */ " insertps " ,
/* 0E8 */ " insw " ,
/* 0E9 */ " int " ,
/* 0EA */ " int1 " ,
/* 0EB */ " int3 " ,
/* 0EC */ " into " ,
/* 0ED */ " invd " ,
/* 0EE */ " invept " ,
/* 0EF */ " invlpg " ,
/* 0F0 */ " invlpga " ,
/* 0F1 */ " invvpid " ,
/* 0F2 */ " iretd " ,
/* 0F3 */ " iretq " ,
/* 0F4 */ " iretw " ,
/* 0F5 */ " ja " ,
2014-10-30 23:36:25 +08:00
/* 0F6 */ " jb " ,
/* 0F7 */ " jbe " ,
/* 0F8 */ " jcxz " ,
/* 0F9 */ " je " ,
/* 0FA */ " jecxz " ,
/* 0FB */ " jg " ,
/* 0FC */ " jge " ,
/* 0FD */ " jl " ,
/* 0FE */ " jle " ,
/* 0FF */ " jmp " ,
/* 100 */ " jnb " ,
2014-10-27 21:10:22 +08:00
/* 101 */ " jne " ,
/* 102 */ " jno " ,
/* 103 */ " jnp " ,
/* 104 */ " jns " ,
/* 105 */ " jo " ,
/* 106 */ " jp " ,
/* 107 */ " jrcxz " ,
/* 108 */ " js " ,
/* 109 */ " lahf " ,
/* 10A */ " lar " ,
/* 10B */ " lddqu " ,
/* 10C */ " ldmxcsr " ,
/* 10D */ " lds " ,
/* 10E */ " lea " ,
/* 10F */ " leave " ,
/* 110 */ " les " ,
/* 111 */ " lfence " ,
/* 112 */ " lfs " ,
/* 113 */ " lgdt " ,
/* 114 */ " lgs " ,
/* 115 */ " lidt " ,
/* 116 */ " lldt " ,
/* 117 */ " lmsw " ,
/* 118 */ " lock " ,
/* 119 */ " lodsb " ,
/* 11A */ " lodsd " ,
/* 11B */ " lodsq " ,
/* 11C */ " lodsw " ,
/* 11D */ " loop " ,
/* 11E */ " loope " ,
/* 11F */ " loopne " ,
/* 120 */ " lsl " ,
/* 121 */ " lss " ,
/* 122 */ " ltr " ,
/* 123 */ " maskmovdqu " ,
/* 124 */ " maskmovq " ,
/* 125 */ " maxpd " ,
/* 126 */ " maxps " ,
/* 127 */ " maxsd " ,
/* 128 */ " maxss " ,
/* 129 */ " mfence " ,
/* 12A */ " minpd " ,
/* 12B */ " minps " ,
/* 12C */ " minsd " ,
/* 12D */ " minss " ,
/* 12E */ " monitor " ,
/* 12F */ " montmul " ,
/* 130 */ " mov " ,
/* 131 */ " movapd " ,
/* 132 */ " movaps " ,
/* 133 */ " movbe " ,
/* 134 */ " movd " ,
/* 135 */ " movddup " ,
/* 136 */ " movdq2q " ,
/* 137 */ " movdqa " ,
/* 138 */ " movdqu " ,
/* 139 */ " movhlps " ,
/* 13A */ " movhpd " ,
/* 13B */ " movhps " ,
/* 13C */ " movlhps " ,
/* 13D */ " movlpd " ,
/* 13E */ " movlps " ,
/* 13F */ " movmskpd " ,
/* 140 */ " movmskps " ,
/* 141 */ " movntdq " ,
/* 142 */ " movntdqa " ,
/* 143 */ " movnti " ,
/* 144 */ " movntpd " ,
/* 145 */ " movntps " ,
/* 146 */ " movntq " ,
/* 147 */ " movq " ,
/* 148 */ " movq2dq " ,
/* 149 */ " movsb " ,
/* 14A */ " movsd " ,
/* 14B */ " movshdup " ,
/* 14C */ " movsldup " ,
/* 14D */ " movsq " ,
/* 14E */ " movss " ,
/* 14F */ " movsw " ,
/* 150 */ " movsx " ,
/* 151 */ " movsxd " ,
/* 152 */ " movupd " ,
/* 153 */ " movups " ,
/* 154 */ " movzx " ,
/* 155 */ " mpsadbw " ,
/* 156 */ " mul " ,
/* 157 */ " mulpd " ,
/* 158 */ " mulps " ,
/* 159 */ " mulsd " ,
/* 15A */ " mulss " ,
/* 15B */ " mwait " ,
/* 15C */ " neg " ,
/* 15D */ " nop " ,
/* 15E */ " not " ,
/* 15F */ " or " ,
/* 160 */ " orpd " ,
/* 161 */ " orps " ,
/* 162 */ " out " ,
/* 163 */ " outsb " ,
/* 164 */ " outsd " ,
/* 165 */ " outsw " ,
/* 166 */ " pabsb " ,
/* 167 */ " pabsd " ,
/* 168 */ " pabsw " ,
/* 169 */ " packssdw " ,
/* 16A */ " packsswb " ,
/* 16B */ " packusdw " ,
/* 16C */ " packuswb " ,
/* 16D */ " paddb " ,
/* 16E */ " paddd " ,
/* 16F */ " paddq " ,
/* 170 */ " paddsb " ,
/* 171 */ " paddsw " ,
/* 172 */ " paddusb " ,
/* 173 */ " paddusw " ,
/* 174 */ " paddw " ,
/* 175 */ " palignr " ,
/* 176 */ " pand " ,
/* 177 */ " pandn " ,
/* 178 */ " pause " ,
/* 179 */ " pavgb " ,
/* 17A */ " pavgusb " ,
/* 17B */ " pavgw " ,
/* 17C */ " pblendvb " ,
/* 17D */ " pblendw " ,
/* 17E */ " pclmulqdq " ,
/* 17F */ " pcmpeqb " ,
/* 180 */ " pcmpeqd " ,
/* 181 */ " pcmpeqq " ,
/* 182 */ " pcmpeqw " ,
/* 183 */ " pcmpestri " ,
/* 184 */ " pcmpestrm " ,
/* 185 */ " pcmpgtb " ,
/* 186 */ " pcmpgtd " ,
/* 187 */ " pcmpgtq " ,
/* 188 */ " pcmpgtw " ,
/* 189 */ " pcmpistri " ,
/* 18A */ " pcmpistrm " ,
/* 18B */ " pextrb " ,
/* 18C */ " pextrd " ,
/* 18D */ " pextrq " ,
/* 18E */ " pextrw " ,
/* 18F */ " pf2id " ,
/* 190 */ " pf2iw " ,
/* 191 */ " pfacc " ,
/* 192 */ " pfadd " ,
/* 193 */ " pfcmpeq " ,
/* 194 */ " pfcmpge " ,
/* 195 */ " pfcmpgt " ,
/* 196 */ " pfmax " ,
/* 197 */ " pfmin " ,
/* 198 */ " pfmul " ,
/* 199 */ " pfnacc " ,
/* 19A */ " pfpnacc " ,
/* 19B */ " pfrcp " ,
/* 19C */ " pfrcpit1 " ,
/* 19D */ " pfrcpit2 " ,
/* 19E */ " pfrsqit1 " ,
/* 19F */ " pfrsqrt " ,
/* 1A0 */ " pfsub " ,
/* 1A1 */ " pfsubr " ,
/* 1A2 */ " phaddd " ,
/* 1A3 */ " phaddsw " ,
/* 1A4 */ " phaddw " ,
/* 1A5 */ " phminposuw " ,
/* 1A6 */ " phsubd " ,
/* 1A7 */ " phsubsw " ,
/* 1A8 */ " phsubw " ,
/* 1A9 */ " pi2fd " ,
/* 1AA */ " pi2fw " ,
/* 1AB */ " pinsrb " ,
/* 1AC */ " pinsrd " ,
/* 1AD */ " pinsrq " ,
/* 1AE */ " pinsrw " ,
/* 1AF */ " pmaddubsw " ,
/* 1B0 */ " pmaddwd " ,
/* 1B1 */ " pmaxsb " ,
/* 1B2 */ " pmaxsd " ,
/* 1B3 */ " pmaxsw " ,
/* 1B4 */ " pmaxub " ,
/* 1B5 */ " pmaxud " ,
/* 1B6 */ " pmaxuw " ,
/* 1B7 */ " pminsb " ,
/* 1B8 */ " pminsd " ,
/* 1B9 */ " pminsw " ,
/* 1BA */ " pminub " ,
/* 1BB */ " pminud " ,
/* 1BC */ " pminuw " ,
/* 1BD */ " pmovmskb " ,
/* 1BE */ " pmovsxbd " ,
/* 1BF */ " pmovsxbq " ,
/* 1C0 */ " pmovsxbw " ,
/* 1C1 */ " pmovsxdq " ,
/* 1C2 */ " pmovsxwd " ,
/* 1C3 */ " pmovsxwq " ,
/* 1C4 */ " pmovzxbd " ,
/* 1C5 */ " pmovzxbq " ,
/* 1C6 */ " pmovzxbw " ,
/* 1C7 */ " pmovzxdq " ,
/* 1C8 */ " pmovzxwd " ,
/* 1C9 */ " pmovzxwq " ,
/* 1CA */ " pmuldq " ,
/* 1CB */ " pmulhrsw " ,
/* 1CC */ " pmulhrw " ,
/* 1CD */ " pmulhuw " ,
/* 1CE */ " pmulhw " ,
/* 1CF */ " pmulld " ,
/* 1D0 */ " pmullw " ,
/* 1D1 */ " pmuludq " ,
/* 1D2 */ " pop " ,
/* 1D3 */ " popa " ,
/* 1D4 */ " popad " ,
/* 1D5 */ " popcnt " ,
/* 1D6 */ " popfd " ,
/* 1D7 */ " popfq " ,
/* 1D8 */ " popfw " ,
/* 1D9 */ " por " ,
/* 1DA */ " prefetch " ,
/* 1DB */ " prefetchnta " ,
/* 1DC */ " prefetcht0 " ,
/* 1DD */ " prefetcht1 " ,
/* 1DE */ " prefetcht2 " ,
/* 1DF */ " psadbw " ,
/* 1E0 */ " pshufb " ,
/* 1E1 */ " pshufd " ,
/* 1E2 */ " pshufhw " ,
/* 1E3 */ " pshuflw " ,
/* 1E4 */ " pshufw " ,
/* 1E5 */ " psignb " ,
/* 1E6 */ " psignd " ,
/* 1E7 */ " psignw " ,
/* 1E8 */ " pslld " ,
/* 1E9 */ " pslldq " ,
/* 1EA */ " psllq " ,
/* 1EB */ " psllw " ,
/* 1EC */ " psrad " ,
/* 1ED */ " psraw " ,
/* 1EE */ " psrld " ,
/* 1EF */ " psrldq " ,
/* 1F0 */ " psrlq " ,
/* 1F1 */ " psrlw " ,
/* 1F2 */ " psubb " ,
/* 1F3 */ " psubd " ,
/* 1F4 */ " psubq " ,
/* 1F5 */ " psubsb " ,
/* 1F6 */ " psubsw " ,
/* 1F7 */ " psubusb " ,
/* 1F8 */ " psubusw " ,
/* 1F9 */ " psubw " ,
/* 1FA */ " pswapd " ,
/* 1FB */ " ptest " ,
/* 1FC */ " punpckhbw " ,
/* 1FD */ " punpckhdq " ,
/* 1FE */ " punpckhqdq " ,
/* 1FF */ " punpckhwd " ,
/* 200 */ " punpcklbw " ,
/* 201 */ " punpckldq " ,
/* 202 */ " punpcklqdq " ,
/* 203 */ " punpcklwd " ,
/* 204 */ " push " ,
/* 205 */ " pusha " ,
/* 206 */ " pushad " ,
/* 207 */ " pushfd " ,
/* 208 */ " pushfq " ,
/* 209 */ " pushfw " ,
/* 20A */ " pxor " ,
/* 20B */ " rcl " ,
/* 20C */ " rcpps " ,
/* 20D */ " rcpss " ,
/* 20E */ " rcr " ,
/* 20F */ " rdmsr " ,
/* 210 */ " rdpmc " ,
/* 211 */ " rdrand " ,
/* 212 */ " rdtsc " ,
/* 213 */ " rdtscp " ,
/* 214 */ " rep " ,
/* 215 */ " repne " ,
/* 216 */ " ret " ,
/* 217 */ " retf " ,
/* 218 */ " rol " ,
/* 219 */ " ror " ,
/* 21A */ " roundpd " ,
/* 21B */ " roundps " ,
/* 21C */ " roundsd " ,
/* 21D */ " roundss " ,
/* 21E */ " rsm " ,
/* 21F */ " rsqrtps " ,
/* 220 */ " rsqrtss " ,
/* 221 */ " sahf " ,
/* 222 */ " salc " ,
/* 223 */ " sar " ,
/* 224 */ " sbb " ,
/* 225 */ " scasb " ,
/* 226 */ " scasd " ,
/* 227 */ " scasq " ,
/* 228 */ " scasw " ,
/* 229 */ " seta " ,
/* 22A */ " setae " ,
/* 22B */ " setb " ,
/* 22C */ " setbe " ,
/* 22D */ " sete " ,
/* 22E */ " setg " ,
/* 22F */ " setge " ,
/* 230 */ " setl " ,
/* 231 */ " setle " ,
/* 232 */ " setne " ,
/* 233 */ " setno " ,
/* 234 */ " setnp " ,
/* 235 */ " setns " ,
/* 236 */ " seto " ,
/* 237 */ " setp " ,
/* 238 */ " sets " ,
/* 239 */ " sfence " ,
/* 23A */ " sgdt " ,
/* 23B */ " shl " ,
/* 23C */ " shld " ,
/* 23D */ " shr " ,
/* 23E */ " shrd " ,
/* 23F */ " shufpd " ,
/* 240 */ " shufps " ,
/* 241 */ " sidt " ,
/* 242 */ " skinit " ,
/* 243 */ " sldt " ,
/* 244 */ " smsw " ,
/* 245 */ " sqrtpd " ,
/* 246 */ " sqrtps " ,
/* 247 */ " sqrtsd " ,
/* 248 */ " sqrtss " ,
/* 249 */ " stc " ,
/* 24A */ " std " ,
/* 24B */ " stgi " ,
/* 24C */ " sti " ,
/* 24D */ " stmxcsr " ,
/* 24E */ " stosb " ,
/* 24F */ " stosd " ,
/* 250 */ " stosq " ,
/* 251 */ " stosw " ,
/* 252 */ " str " ,
/* 253 */ " sub " ,
/* 254 */ " subpd " ,
/* 255 */ " subps " ,
/* 256 */ " subsd " ,
/* 257 */ " subss " ,
/* 258 */ " swapgs " ,
/* 259 */ " syscall " ,
/* 25A */ " sysenter " ,
/* 25B */ " sysexit " ,
/* 25C */ " sysret " ,
/* 25D */ " test " ,
/* 25E */ " ucomisd " ,
/* 25F */ " ucomiss " ,
/* 260 */ " ud2 " ,
/* 261 */ " unpckhpd " ,
/* 262 */ " unpckhps " ,
/* 263 */ " unpcklpd " ,
/* 264 */ " unpcklps " ,
/* 265 */ " vaddpd " ,
/* 266 */ " vaddps " ,
/* 267 */ " vaddsd " ,
/* 268 */ " vaddss " ,
/* 269 */ " vaddsubpd " ,
/* 26A */ " vaddsubps " ,
/* 26B */ " vaesdec " ,
/* 26C */ " vaesdeclast " ,
/* 26D */ " vaesenc " ,
/* 26E */ " vaesenclast " ,
/* 26F */ " vaesimc " ,
/* 270 */ " vaeskeygenassist " ,
/* 271 */ " vandnpd " ,
/* 272 */ " vandnps " ,
/* 273 */ " vandpd " ,
/* 274 */ " vandps " ,
/* 275 */ " vblendpd " ,
/* 276 */ " vblendps " ,
/* 277 */ " vblendvpd " ,
/* 278 */ " vblendvps " ,
/* 279 */ " vbroadcastsd " ,
/* 27A */ " vbroadcastss " ,
/* 27B */ " vcmppd " ,
/* 27C */ " vcmpps " ,
/* 27D */ " vcmpsd " ,
/* 27E */ " vcmpss " ,
/* 27F */ " vcomisd " ,
/* 280 */ " vcomiss " ,
/* 281 */ " vcvtdq2pd " ,
/* 282 */ " vcvtdq2ps " ,
/* 283 */ " vcvtpd2dq " ,
/* 284 */ " vcvtpd2ps " ,
/* 285 */ " vcvtps2dq " ,
/* 286 */ " vcvtps2pd " ,
/* 287 */ " vcvtsd2si " ,
/* 288 */ " vcvtsd2ss " ,
/* 289 */ " vcvtsi2sd " ,
/* 28A */ " vcvtsi2ss " ,
/* 28B */ " vcvtss2sd " ,
/* 28C */ " vcvtss2si " ,
/* 28D */ " vcvttpd2dq " ,
/* 28E */ " vcvttps2dq " ,
/* 28F */ " vcvttsd2si " ,
/* 290 */ " vcvttss2si " ,
/* 291 */ " vdivpd " ,
/* 292 */ " vdivps " ,
/* 293 */ " vdivsd " ,
/* 294 */ " vdivss " ,
/* 295 */ " vdppd " ,
/* 296 */ " vdpps " ,
/* 297 */ " verr " ,
/* 298 */ " verw " ,
/* 299 */ " vextractf128 " ,
/* 29A */ " vextractps " ,
/* 29B */ " vhaddpd " ,
/* 29C */ " vhaddps " ,
/* 29D */ " vhsubpd " ,
/* 29E */ " vhsubps " ,
/* 29F */ " vinsertf128 " ,
/* 2A0 */ " vinsertps " ,
/* 2A1 */ " vlddqu " ,
/* 2A2 */ " vmaskmovdqu " ,
/* 2A3 */ " vmaskmovpd " ,
/* 2A4 */ " vmaskmovps " ,
/* 2A5 */ " vmaxpd " ,
/* 2A6 */ " vmaxps " ,
/* 2A7 */ " vmaxsd " ,
/* 2A8 */ " vmaxss " ,
/* 2A9 */ " vmcall " ,
/* 2AA */ " vmclear " ,
/* 2AB */ " vminpd " ,
/* 2AC */ " vminps " ,
/* 2AD */ " vminsd " ,
/* 2AE */ " vminss " ,
/* 2AF */ " vmlaunch " ,
/* 2B0 */ " vmload " ,
/* 2B1 */ " vmmcall " ,
/* 2B2 */ " vmovapd " ,
/* 2B3 */ " vmovaps " ,
/* 2B4 */ " vmovd " ,
/* 2B5 */ " vmovddup " ,
/* 2B6 */ " vmovdqa " ,
/* 2B7 */ " vmovdqu " ,
/* 2B8 */ " vmovhlps " ,
/* 2B9 */ " vmovhpd " ,
/* 2BA */ " vmovhps " ,
/* 2BB */ " vmovlhps " ,
/* 2BC */ " vmovlpd " ,
/* 2BD */ " vmovlps " ,
/* 2BE */ " vmovmskpd " ,
/* 2BF */ " vmovmskps " ,
/* 2C0 */ " vmovntdq " ,
/* 2C1 */ " vmovntdqa " ,
/* 2C2 */ " vmovntpd " ,
/* 2C3 */ " vmovntps " ,
/* 2C4 */ " vmovq " ,
/* 2C5 */ " vmovsd " ,
/* 2C6 */ " vmovshdup " ,
/* 2C7 */ " vmovsldup " ,
/* 2C8 */ " vmovss " ,
/* 2C9 */ " vmovupd " ,
/* 2CA */ " vmovups " ,
/* 2CB */ " vmpsadbw " ,
/* 2CC */ " vmptrld " ,
/* 2CD */ " vmptrst " ,
/* 2CE */ " vmread " ,
/* 2CF */ " vmresume " ,
/* 2D0 */ " vmrun " ,
/* 2D1 */ " vmsave " ,
/* 2D2 */ " vmulpd " ,
/* 2D3 */ " vmulps " ,
/* 2D4 */ " vmulsd " ,
/* 2D5 */ " vmulss " ,
/* 2D6 */ " vmwrite " ,
/* 2D7 */ " vmxoff " ,
/* 2D8 */ " vmxon " ,
/* 2D9 */ " vorpd " ,
/* 2DA */ " vorps " ,
/* 2DB */ " vpabsb " ,
/* 2DC */ " vpabsd " ,
/* 2DD */ " vpabsw " ,
/* 2DE */ " vpackssdw " ,
/* 2DF */ " vpacksswb " ,
/* 2E0 */ " vpackusdw " ,
/* 2E1 */ " vpackuswb " ,
/* 2E2 */ " vpaddb " ,
/* 2E3 */ " vpaddd " ,
/* 2E4 */ " vpaddq " ,
/* 2E5 */ " vpaddsb " ,
/* 2E6 */ " vpaddsw " ,
/* 2E7 */ " vpaddusb " ,
/* 2E8 */ " vpaddusw " ,
/* 2E9 */ " vpaddw " ,
/* 2EA */ " vpalignr " ,
/* 2EB */ " vpand " ,
/* 2EC */ " vpandn " ,
/* 2ED */ " vpavgb " ,
/* 2EE */ " vpavgw " ,
/* 2EF */ " vpblendvb " ,
/* 2F0 */ " vpblendw " ,
/* 2F1 */ " vpclmulqdq " ,
/* 2F2 */ " vpcmpeqb " ,
/* 2F3 */ " vpcmpeqd " ,
/* 2F4 */ " vpcmpeqq " ,
/* 2F5 */ " vpcmpeqw " ,
/* 2F6 */ " vpcmpestri " ,
/* 2F7 */ " vpcmpestrm " ,
/* 2F8 */ " vpcmpgtb " ,
/* 2F9 */ " vpcmpgtd " ,
/* 2FA */ " vpcmpgtq " ,
/* 2FB */ " vpcmpgtw " ,
/* 2FC */ " vpcmpistri " ,
/* 2FD */ " vpcmpistrm " ,
/* 2FE */ " vperm2f128 " ,
/* 2FF */ " vpermilpd " ,
/* 300 */ " vpermilps " ,
/* 301 */ " vpextrb " ,
/* 302 */ " vpextrd " ,
/* 303 */ " vpextrq " ,
/* 304 */ " vpextrw " ,
/* 305 */ " vphaddd " ,
/* 306 */ " vphaddsw " ,
/* 307 */ " vphaddw " ,
/* 308 */ " vphminposuw " ,
/* 309 */ " vphsubd " ,
/* 30A */ " vphsubsw " ,
/* 30B */ " vphsubw " ,
/* 30C */ " vpinsrb " ,
/* 30D */ " vpinsrd " ,
/* 30E */ " vpinsrq " ,
/* 30F */ " vpinsrw " ,
/* 310 */ " vpmaddubsw " ,
/* 311 */ " vpmaddwd " ,
/* 312 */ " vpmaxsb " ,
/* 313 */ " vpmaxsd " ,
/* 314 */ " vpmaxsw " ,
/* 315 */ " vpmaxub " ,
/* 316 */ " vpmaxud " ,
/* 317 */ " vpmaxuw " ,
/* 318 */ " vpminsb " ,
/* 319 */ " vpminsd " ,
/* 31A */ " vpminsw " ,
/* 31B */ " vpminub " ,
/* 31C */ " vpminud " ,
/* 31D */ " vpminuw " ,
/* 31E */ " vpmovmskb " ,
/* 31F */ " vpmovsxbd " ,
/* 320 */ " vpmovsxbq " ,
/* 321 */ " vpmovsxbw " ,
/* 322 */ " vpmovsxwd " ,
/* 323 */ " vpmovsxwq " ,
/* 324 */ " vpmovzxbd " ,
/* 325 */ " vpmovzxbq " ,
/* 326 */ " vpmovzxbw " ,
/* 327 */ " vpmovzxdq " ,
/* 328 */ " vpmovzxwd " ,
/* 329 */ " vpmovzxwq " ,
/* 32A */ " vpmuldq " ,
/* 32B */ " vpmulhrsw " ,
/* 32C */ " vpmulhuw " ,
/* 32D */ " vpmulhw " ,
/* 32E */ " vpmulld " ,
/* 32F */ " vpmullw " ,
/* 330 */ " vpor " ,
/* 331 */ " vpsadbw " ,
/* 332 */ " vpshufb " ,
/* 333 */ " vpshufd " ,
/* 334 */ " vpshufhw " ,
/* 335 */ " vpshuflw " ,
/* 336 */ " vpsignb " ,
/* 337 */ " vpsignd " ,
/* 338 */ " vpsignw " ,
/* 339 */ " vpslld " ,
/* 33A */ " vpslldq " ,
/* 33B */ " vpsllq " ,
/* 33C */ " vpsllw " ,
/* 33D */ " vpsrad " ,
/* 33E */ " vpsraw " ,
/* 33F */ " vpsrld " ,
/* 340 */ " vpsrldq " ,
/* 341 */ " vpsrlq " ,
/* 342 */ " vpsrlw " ,
/* 343 */ " vpsubb " ,
/* 344 */ " vpsubd " ,
/* 345 */ " vpsubq " ,
/* 346 */ " vpsubsb " ,
/* 347 */ " vpsubsw " ,
/* 348 */ " vpsubusb " ,
/* 349 */ " vpsubusw " ,
/* 34A */ " vpsubw " ,
/* 34B */ " vptest " ,
/* 34C */ " vpunpckhbw " ,
/* 34D */ " vpunpckhdq " ,
/* 34E */ " vpunpckhqdq " ,
/* 34F */ " vpunpckhwd " ,
/* 350 */ " vpunpcklbw " ,
/* 351 */ " vpunpckldq " ,
/* 352 */ " vpunpcklqdq " ,
/* 353 */ " vpunpcklwd " ,
/* 354 */ " vpxor " ,
/* 355 */ " vrcpps " ,
/* 356 */ " vrcpss " ,
/* 357 */ " vroundpd " ,
/* 358 */ " vroundps " ,
/* 359 */ " vroundsd " ,
/* 35A */ " vroundss " ,
/* 35B */ " vrsqrtps " ,
/* 35C */ " vrsqrtss " ,
/* 35D */ " vshufpd " ,
/* 35E */ " vshufps " ,
/* 35F */ " vsqrtpd " ,
/* 360 */ " vsqrtps " ,
/* 361 */ " vsqrtsd " ,
/* 362 */ " vsqrtss " ,
/* 363 */ " vstmxcsr " ,
/* 364 */ " vsubpd " ,
/* 365 */ " vsubps " ,
/* 366 */ " vsubsd " ,
/* 367 */ " vsubss " ,
/* 368 */ " vtestpd " ,
/* 369 */ " vtestps " ,
/* 36A */ " vucomisd " ,
/* 36B */ " vucomiss " ,
/* 36C */ " vunpckhpd " ,
/* 36D */ " vunpckhps " ,
/* 36E */ " vunpcklpd " ,
/* 36F */ " vunpcklps " ,
/* 370 */ " vxorpd " ,
/* 371 */ " vxorps " ,
/* 372 */ " vzeroall " ,
/* 373 */ " vzeroupper " ,
/* 374 */ " wait " ,
/* 375 */ " wbinvd " ,
/* 376 */ " wrmsr " ,
/* 377 */ " xadd " ,
/* 378 */ " xchg " ,
/* 379 */ " xcryptcbc " ,
/* 37A */ " xcryptcfb " ,
/* 37B */ " xcryptctr " ,
/* 37C */ " xcryptecb " ,
/* 37D */ " xcryptofb " ,
/* 37E */ " xgetbv " ,
/* 37F */ " xlatb " ,
/* 380 */ " xor " ,
/* 381 */ " xorpd " ,
/* 382 */ " xorps " ,
/* 383 */ " xrstor " ,
/* 384 */ " xsave " ,
/* 385 */ " xsetbv " ,
/* 386 */ " xsha1 " ,
/* 387 */ " xsha256 " ,
/* 388 */ " xstore " ,
2014-10-25 05:11:16 +08:00
} ;
}
}