From 983f7b507a32a890d6fb7c3d4995266b16decb7f Mon Sep 17 00:00:00 2001 From: mrexodia Date: Sun, 9 Oct 2016 15:05:25 +0200 Subject: [PATCH] PROJECT: fixed duplicate mnemonics in mnemdb.json --- bin/mnemdb.json | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/bin/mnemdb.json b/bin/mnemdb.json index 3b0e7887..4f0755d5 100644 --- a/bin/mnemdb.json +++ b/bin/mnemdb.json @@ -229,7 +229,7 @@ "mnem": "CMPPS" }, { - "description": "\nCMPS/CMPSB/CMPSW/CMPSD/CMPSQ - Compare String Operands:\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| A6 | CMPS m8, m8 | NP | Valid | Valid | For legacy mode, compare byte at address \n| | | | | | DS:(E)SI with byte at address ES:(E)DI; \n| | | | | | For 64bit mode compare byte at address \n| | | | | | (R|E)SI to byte at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPS m16, m16| NP | Valid | Valid | For legacy mode, compare word at address \n| | | | | | DS:(E)SI with word at address ES:(E)DI; \n| | | | | | For 64bit mode compare word at address \n| | | | | | (R|E)SI with word at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPS m32, m32| NP | Valid | Valid | For legacy mode, compare dword at address\n| | | | | | DS:(E)SI at dword at address ES:(E)DI; \n| | | | | | For 64bit mode compare dword at address \n| | | | | | (R|E)SI at dword at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| REX.W + A7| CMPS m64, m64| NP | Valid | N.E. | Compares quadword at address (R|E)SI \n| | | | | | with quadword at address (R|E)DI and \n| | | | | | sets the status flags accordingly. \n| A6 | CMPSB | NP | Valid | Valid | For legacy mode, compare byte at address \n| | | | | | DS:(E)SI with byte at address ES:(E)DI; \n| | | | | | For 64bit mode compare byte at address \n| | | | | | (R|E)SI with byte at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPSW | NP | Valid | Valid | For legacy mode, compare word at address \n| | | | | | DS:(E)SI with word at address ES:(E)DI; \n| | | | | | For 64bit mode compare word at address \n| | | | | | (R|E)SI with word at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPSD | NP | Valid | Valid | For legacy mode, compare dword at address\n| | | | | | DS:(E)SI with dword at address ES:(E)DI; \n| | | | | | For 64-bit mode compare dword at address \n| | | | | | (R|E)SI with dword at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| REX.W + A7| CMPSQ | NP | Valid | N.E. | Compares quadword at address (R|E)SI \n| | | | | | with quadword at address (R|E)DI and \n| | | | | | sets the status flags accordingly. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1| Operand 2| Operand 3| Operand 4\n| NP | NA | NA | NA | NA \n\nDescription:\nCompares the byte, word, doubleword, or quadword specified with the first source\noperand with the byte, word, doubleword, or quadword specified with the second\nsource operand and sets the status flags in the EFLAGS register according to\nthe results.\n\nBoth source operands are located in memory. The address of the first source\noperand is read from DS:SI, DS:ESI or RSI (depending on the address-size attribute\nof the instruction is 16, 32, or 64, respectively). The address of the second\nsource operand is read from ES:DI, ES:EDI or RDI (again depending on the address-size\nattribute of the\n\ninstruction is 16, 32, or 64). The DS segment may be overridden with a segment\noverride prefix, but the ES segment cannot be overridden.\n\nAt the assembly-code level, two forms of this instruction are allowed: the \u201cexplicit-operands\u201d\nform and the \u201cnooperands\u201d form. The explicit-operands form (specified with the\nCMPS mnemonic) allows the two source operands to be specified explicitly. Here,\nthe source operands should be symbols that indicate the size and location of\nthe source values. This explicit-operand form is provided to allow documentation.\nHowever, note that the documentation provided by this form can be misleading.\nThat is, the source operand symbols must specify the correct type (size) of\nthe operands (bytes, words, or doublewords, quadwords), but they do not have\nto specify the correct location. Locations of the source operands are always\nspecified by the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers, which must\nbe loaded correctly before the compare string instruction is executed.\n\nThe no-operands form provides \u201cshort forms\u201d of the byte, word, and doubleword\nversions of the CMPS instructions. Here also the DS:(E)SI (or RSI) and ES:(E)DI\n(or RDI) registers are assumed by the processor to specify the location of the\nsource operands. The size of the source operands is selected with the mnemonic:\nCMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison),\nor CMPSQ (quadword comparison using REX.W).\n\nAfter the comparison, the (E/R)SI and (E/R)DI registers increment or decrement\nautomatically according to the setting of the DF flag in the EFLAGS register.\n(If the DF flag is 0, the (E/R)SI and (E/R)DI register increment; if the DF\nflag is 1, the registers decrement.) The registers increment or decrement by\n1 for byte operations, by 2 for word operations, 4 for doubleword operations.\nIf operand size is 64, RSI and RDI registers increment by 8 for quadword operations.\n\nThe CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the\nREP prefix for block comparisons. More often, however, these instructions will\nbe used in a LOOP construct that takes some action based on the setting of the\nstatus flags before the next comparison is made. See \u201cREP/REPE/REPZ /REPNE/REPNZ - Repeat\nString Operation Prefix\u201d in Chapter 4 of the Intel\u00ae 64 and IA-32 Architectures\nSoftware Developer's Manual, Volume 2B, for a description of the REP prefix.\n\nIn 64-bit mode, the instruction's default address size is 64 bits, 32 bit address\nsize is supported using the prefix 67H. Use of the REX.W prefix promotes doubleword\noperation to 64 bits (see CMPSQ). See the summary chart at the beginning of\nthis section for encoding data and limits.\n\nOperation:\n\ntemp <- SRC1 - SRC2;\nSetStatusFlags(temp);\nIF (64-Bit Mode)\n THEN\n IF (Byte comparison)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 1;\n (R|E)DI <- (R|E)DI + 1;\n ELSE\n (R|E)SI <- (R|E)SI - 1;\n (R|E)DI <- (R|E)DI - 1;\n FI;\n ELSE IF (Word comparison)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 2;\n (R|E)DI <- (R|E)DI + 2;\n ELSE\n (R|E)SI <- (R|E)SI - 2;\n (R|E)DI <- (R|E)DI - 2;\n FI;\n ELSE IF (Doubleword comparison)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 4;\n (R|E)DI <- (R|E)DI + 4;\n ELSE\n (R|E)SI <- (R|E)SI - 4;\n (R|E)DI <- (R|E)DI - 4;\n FI;\n ELSE (* Quadword comparison *)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 8;\n (R|E)DI <- (R|E)DI + 8;\n ELSE\n (R|E)SI <- (R|E)SI - 8;\n (R|E)DI <- (R|E)DI - 8;\n FI;\n FI;\n ELSE (* Non-64-bit Mode *)\n IF (byte comparison)\n THEN IF DF = 0\n THEN\n (E)SI <- (E)SI + 1;\n (E)DI <- (E)DI + 1;\n ELSE\n (E)SI <- (E)SI - 1;\n (E)DI <- (E)DI - 1;\n FI;\n ELSE IF (Word comparison)\n THEN IF DF = 0\n (E)SI <- (E)SI + 2;\n (E)DI <- (E)DI + 2;\n ELSE\n (E)SI <- (E)SI - 2;\n (E)DI <- (E)DI - 2;\n FI;\n ELSE (* Doubleword comparison *)\n THEN IF DF = 0\n (E)SI <- (E)SI + 4;\n (E)DI <- (E)DI + 4;\n ELSE\n (E)SI <- (E)SI - 4;\n (E)DI <- (E)DI - 4;\n FI;\n FI;\nFI;\n\nFlags Affected:\nThe CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result\nof the comparison.\n\n\nProtected Mode Exceptions:\n| #GP(0) | If a memory operand effective address\n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. If the DS, ES, FS, or \n| | GS register contains a NULL segment \n| | selector. \n| #SS(0) | If a memory operand effective address\n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made\n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n\nReal-Address Mode Exceptions:\n| #GP| If a memory operand effective address\n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS| If a memory operand effective address\n| | is outside the SS segment limit. \n| #UD| If the LOCK prefix is used. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0) | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made.\n| #UD | If the LOCK prefix is used. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #SS(0) | If a memory address referencing the \n| | SS segment is in a non-canonical form. \n| #GP(0) | If the memory address is in a non-canonical\n| | form. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n", + "description": "\nCMPS/CMPSB/CMPSW/CMPSD/CMPSQ - Compare String Operands:\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| A6 | CMPS m8, m8 | NP | Valid | Valid | For legacy mode, compare byte at address \n| | | | | | DS:(E)SI with byte at address ES:(E)DI; \n| | | | | | For 64bit mode compare byte at address \n| | | | | | (R|E)SI to byte at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPS m16, m16| NP | Valid | Valid | For legacy mode, compare word at address \n| | | | | | DS:(E)SI with word at address ES:(E)DI; \n| | | | | | For 64bit mode compare word at address \n| | | | | | (R|E)SI with word at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPS m32, m32| NP | Valid | Valid | For legacy mode, compare dword at address\n| | | | | | DS:(E)SI at dword at address ES:(E)DI; \n| | | | | | For 64bit mode compare dword at address \n| | | | | | (R|E)SI at dword at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| REX.W + A7| CMPS m64, m64| NP | Valid | N.E. | Compares quadword at address (R|E)SI \n| | | | | | with quadword at address (R|E)DI and \n| | | | | | sets the status flags accordingly. \n| A6 | CMPSB | NP | Valid | Valid | For legacy mode, compare byte at address \n| | | | | | DS:(E)SI with byte at address ES:(E)DI; \n| | | | | | For 64bit mode compare byte at address \n| | | | | | (R|E)SI with byte at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPSW | NP | Valid | Valid | For legacy mode, compare word at address \n| | | | | | DS:(E)SI with word at address ES:(E)DI; \n| | | | | | For 64bit mode compare word at address \n| | | | | | (R|E)SI with word at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| A7 | CMPSD | NP | Valid | Valid | For legacy mode, compare dword at address\n| | | | | | DS:(E)SI with dword at address ES:(E)DI; \n| | | | | | For 64-bit mode compare dword at address \n| | | | | | (R|E)SI with dword at address (R|E)DI. \n| | | | | | The status flags are set accordingly. \n| REX.W + A7| CMPSQ | NP | Valid | N.E. | Compares quadword at address (R|E)SI \n| | | | | | with quadword at address (R|E)DI and \n| | | | | | sets the status flags accordingly. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1| Operand 2| Operand 3| Operand 4\n| NP | NA | NA | NA | NA \n\nDescription:\nCompares the byte, word, doubleword, or quadword specified with the first source\noperand with the byte, word, doubleword, or quadword specified with the second\nsource operand and sets the status flags in the EFLAGS register according to\nthe results.\n\nBoth source operands are located in memory. The address of the first source\noperand is read from DS:SI, DS:ESI or RSI (depending on the address-size attribute\nof the instruction is 16, 32, or 64, respectively). The address of the second\nsource operand is read from ES:DI, ES:EDI or RDI (again depending on the address-size\nattribute of the\n\ninstruction is 16, 32, or 64). The DS segment may be overridden with a segment\noverride prefix, but the ES segment cannot be overridden.\n\nAt the assembly-code level, two forms of this instruction are allowed: the \u201cexplicit-operands\u201d\nform and the \u201cnooperands\u201d form. The explicit-operands form (specified with the\nCMPS mnemonic) allows the two source operands to be specified explicitly. Here,\nthe source operands should be symbols that indicate the size and location of\nthe source values. This explicit-operand form is provided to allow documentation.\nHowever, note that the documentation provided by this form can be misleading.\nThat is, the source operand symbols must specify the correct type (size) of\nthe operands (bytes, words, or doublewords, quadwords), but they do not have\nto specify the correct location. Locations of the source operands are always\nspecified by the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers, which must\nbe loaded correctly before the compare string instruction is executed.\n\nThe no-operands form provides \u201cshort forms\u201d of the byte, word, and doubleword\nversions of the CMPS instructions. Here also the DS:(E)SI (or RSI) and ES:(E)DI\n(or RDI) registers are assumed by the processor to specify the location of the\nsource operands. The size of the source operands is selected with the mnemonic:\nCMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison),\nor CMPSQ (quadword comparison using REX.W).\n\nAfter the comparison, the (E/R)SI and (E/R)DI registers increment or decrement\nautomatically according to the setting of the DF flag in the EFLAGS register.\n(If the DF flag is 0, the (E/R)SI and (E/R)DI register increment; if the DF\nflag is 1, the registers decrement.) The registers increment or decrement by\n1 for byte operations, by 2 for word operations, 4 for doubleword operations.\nIf operand size is 64, RSI and RDI registers increment by 8 for quadword operations.\n\nThe CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the\nREP prefix for block comparisons. More often, however, these instructions will\nbe used in a LOOP construct that takes some action based on the setting of the\nstatus flags before the next comparison is made. See \u201cREP/REPE/REPZ /REPNE/REPNZ - Repeat\nString Operation Prefix\u201d in Chapter 4 of the Intel\u00ae 64 and IA-32 Architectures\nSoftware Developer's Manual, Volume 2B, for a description of the REP prefix.\n\nIn 64-bit mode, the instruction's default address size is 64 bits, 32 bit address\nsize is supported using the prefix 67H. Use of the REX.W prefix promotes doubleword\noperation to 64 bits (see CMPSQ). See the summary chart at the beginning of\nthis section for encoding data and limits.\n\nOperation:\n\ntemp <- SRC1 - SRC2;\nSetStatusFlags(temp);\nIF (64-Bit Mode)\n THEN\n IF (Byte comparison)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 1;\n (R|E)DI <- (R|E)DI + 1;\n ELSE\n (R|E)SI <- (R|E)SI - 1;\n (R|E)DI <- (R|E)DI - 1;\n FI;\n ELSE IF (Word comparison)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 2;\n (R|E)DI <- (R|E)DI + 2;\n ELSE\n (R|E)SI <- (R|E)SI - 2;\n (R|E)DI <- (R|E)DI - 2;\n FI;\n ELSE IF (Doubleword comparison)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 4;\n (R|E)DI <- (R|E)DI + 4;\n ELSE\n (R|E)SI <- (R|E)SI - 4;\n (R|E)DI <- (R|E)DI - 4;\n FI;\n ELSE (* Quadword comparison *)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 8;\n (R|E)DI <- (R|E)DI + 8;\n ELSE\n (R|E)SI <- (R|E)SI - 8;\n (R|E)DI <- (R|E)DI - 8;\n FI;\n FI;\n ELSE (* Non-64-bit Mode *)\n IF (byte comparison)\n THEN IF DF = 0\n THEN\n (E)SI <- (E)SI + 1;\n (E)DI <- (E)DI + 1;\n ELSE\n (E)SI <- (E)SI - 1;\n (E)DI <- (E)DI - 1;\n FI;\n ELSE IF (Word comparison)\n THEN IF DF = 0\n (E)SI <- (E)SI + 2;\n (E)DI <- (E)DI + 2;\n ELSE\n (E)SI <- (E)SI - 2;\n (E)DI <- (E)DI - 2;\n FI;\n ELSE (* Doubleword comparison *)\n THEN IF DF = 0\n (E)SI <- (E)SI + 4;\n (E)DI <- (E)DI + 4;\n ELSE\n (E)SI <- (E)SI - 4;\n (E)DI <- (E)DI - 4;\n FI;\n FI;\nFI;\n\nFlags Affected:\nThe CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result\nof the comparison.\n\n\nProtected Mode Exceptions:\n| #GP(0) | If a memory operand effective address\n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. If the DS, ES, FS, or \n| | GS register contains a NULL segment \n| | selector. \n| #SS(0) | If a memory operand effective address\n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made\n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n\nReal-Address Mode Exceptions:\n| #GP| If a memory operand effective address\n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS| If a memory operand effective address\n| | is outside the SS segment limit. \n| #UD| If the LOCK prefix is used. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0) | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made.\n| #UD | If the LOCK prefix is used. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #SS(0) | If a memory address referencing the \n| | SS segment is in a non-canonical form. \n| #GP(0) | If the memory address is in a non-canonical\n| | form. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n\nCMPSD - Compare Scalar Double-Precision Floating-Point Values:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, | RMI | V/V | SSE2 | Compare low double-precision floating-point\n| imm8 | | | | value in xmm2/m64 and xmm1 using imm8 \n| | | | | as comparison predicate. \n| VEX.NDS.LIG.F2.0F.WIG C2 /r ib VCMPSD| RVMI | V/V | AVX | Compare low double precision floating-point\n| xmm1, xmm2, xmm3/m64, imm8 | | | | value in xmm3/m64 and xmm2 using bits \n| | | | | 4:0 of imm8 as comparison predicate. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3 | Operand 4\n| RMI | ModRM:reg (r, w)| ModRM:r/m (r)| imm8 | NA \n| RVMI | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r)| imm8 \n\nDescription:\nCompares the low double-precision floating-point values in the source operand\n(second operand) and the destination operand (first operand) and returns the\nresults of the comparison to the destination operand. The comparison predicate\noperand (third operand) specifies the type of comparison performed. The comparison\nresult is a quadword mask of all 1s (comparison true) or all 0s (comparison\nfalse). The sign of zero is ignored for comparisons, so that -0.0 is equal to\n+0.0. 128-bit Legacy SSE version: The first source and destination operand (first\noperand) is an XMM register. The second source operand (second operand) can\nbe an XMM register or 64-bit memory location. The comparison predicate operand\nis an 8-bit immediate, bits 2:0 of the immediate define the type of comparison\nto be performed (see Table 3-7). Bits 7:3 of the immediate is reserved. Bits\n(VLMAX-1:64) of the corresponding YMM destination register remain unchanged.\n\nThe unordered relationship is true when at least one of the two source operands\nbeing compared is a NaN; the ordered relationship is true when neither source\noperand is a NaN.\n\nA subsequent computational instruction that uses the mask result in the destination\noperand as an input operand will not generate a fault, because a mask of all\n0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds\nto a QNaN.\n\nNote that processors with \u201cCPUID.1H:ECX.AVX =0\u201d do not implement the \u201cgreater-than\u201d,\n\u201cgreater-than-or-equal\u201d, \u201cnot-greater than\u201d, and \u201cnot-greater-than-or-equal\nrelations\u201d predicates. These comparisons can be made either by using the inverse\nrelationship (that is, use the \u201cnot-less-than-or-equal\u201d to make a \u201cgreater-than\u201d\ncomparison) or by using software emulation. When using software emulation, the\nprogram must swap the operands (copying registers when necessary to protect\nthe data that will now be in the destination operand), and then perform the\ncompare using a different predicate. The predicate to be used for these emulations\nis listed in Table 3-7 under the heading Emulation.\n\nCompilers and assemblers may implement the following two-operand pseudo-ops\nin addition to the three-operand CMPSD instruction, for processors with \u201cCPUID.1H:ECX.AVX\n=0\u201d. See Table 3-13. Compiler should treat reserved Imm8 values as illegal syntax.\n\n\nTable 3-13. Pseudo-Ops and CMPSD:\n| Pseudo-Op | Implementation \n| CMPEQSD xmm1, xmm2 | CMPSD xmm1,xmm2, 0\n| CMPLTSD xmm1, xmm2 | CMPSD xmm1,xmm2, 1\n| CMPLESD xmm1, xmm2 | CMPSD xmm1,xmm2, 2\n| CMPUNORDSD xmm1, xmm2| CMPSD xmm1,xmm2, 3\n| CMPNEQSD xmm1, xmm2 | CMPSD xmm1,xmm2, 4\n| CMPNLTSD xmm1, xmm2 | CMPSD xmm1,xmm2, 5\n| CMPNLESD xmm1, xmm2 | CMPSD xmm1,xmm2, 6\n| CMPORDSD xmm1, xmm2 | CMPSD xmm1,xmm2, 7\nThe greater-than relations not implemented in the processor require more than\none instruction to emulate in software and therefore should not be implemented\nas pseudo-ops. (For these, the programmer should reverse the operands of the\ncorresponding less than relations and use move instructions to ensure that the\nmask is moved to the correct destination register and that the source operand\nis left intact.)\n\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional\nregisters (XMM8-XMM15).\n\nEnhanced Comparison Predicate for VEX-Encoded VCMPSD VEX.128 encoded version:\nThe first source operand (second operand) is an XMM register. The second source\noperand (third operand) can be an XMM register or a 64-bit memory location.\nBits (VLMAX-1:128) of the destination YMM register are zeroed. The comparison\npredicate operand is an 8-bit immediate:\n\n - For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison\nto be performed (see Table 3-9). Bits 5 through 7 of the immediate are reserved.\n\nProcessors with \u201cCPUID.1H:ECX.AVX =1\u201d implement the full complement of 32 predicates\nshown in Table 3-9, software emulation is no longer needed. Compilers and assemblers\nmay implement the following three-operand pseudo-ops in addition to the four-operand\nVCMPSD instruction. See Table 3-14, where the notations of reg1 reg2, and reg3\nrepresent either XMM registers or YMM registers. Compiler should treat reserved\nImm8 values as illegal syntax. Alternately, intrinsics can map the pseudo-ops\nto pre-defined constants to support a simpler intrinsic interface.\n\n| : Pseudo-Op VCMPEQSD reg1, reg2, reg3 | Table 3-14. Table 3-14.| Pseudo-Op and VCMPSD Implementation \n| VCMPLTSD reg1, reg2, reg3 VCMPLESD reg1, | | CMPSD Implementation VCMPSD reg1, reg2, \n| reg2, reg3 VCMPUNORDSD reg1, reg2, reg3 | | reg3, 0 VCMPSD reg1, reg2, reg3, 1 VCMPSD\n| VCMPNEQSD reg1, reg2, reg3 VCMPNLTSD | | reg1, reg2, reg3, 2 VCMPSD reg1, reg2, \n| reg1, reg2, reg3 VCMPNLESD reg1, reg2, | | reg3, 3 VCMPSD reg1, reg2, reg3, 4 VCMPSD\n| reg3 VCMPORDSD reg1, reg2, reg3 VCMPEQ_UQSD | | reg1, reg2, reg3, 5 VCMPSD reg1, reg2, \n| reg1, reg2, reg3 VCMPNGESD reg1, reg2, | | reg3, 6 VCMPSD reg1, reg2, reg3, 7 VCMPSD\n| reg3 VCMPNGTSD reg1, reg2, reg3 VCMPFALSESD | | reg1, reg2, reg3, 8 VCMPSD reg1, reg2, \n| reg1, reg2, reg3 VCMPNEQ_OQSD reg1, | | reg3, 9 VCMPSD reg1, reg2, reg3, 0AH \n| reg2, reg3 VCMPGESD reg1, reg2, reg3 | | VCMPSD reg1, reg2, reg3, 0BH VCMPSD \n| VCMPGTSD reg1, reg2, reg3 Pseudo-Op | | reg1, reg2, reg3, 0CH VCMPSD reg1, reg2, \n| VCMPTRUESD reg1, reg2, reg3 VCMPEQ_OSSD | | reg3, 0DH VCMPSD reg1, reg2, reg3, 0EH \n| reg1, reg2, reg3 VCMPLT_OQSD reg1, reg2, | | Pseudo-Op and VCMPSD Implementation \n| reg3 VCMPLE_OQSD reg1, reg2, reg3 VCMPUNORD_SSD| | (Contd.) CMPSD Implementation VCMPSD \n| reg1, reg2, reg3 VCMPNEQ_USSD reg1, | | reg1, reg2, reg3, 0FH VCMPSD reg1, reg2, \n| reg2, reg3 VCMPNLT_UQSD reg1, reg2, | | reg3, 10H VCMPSD reg1, reg2, reg3, 11H \n| reg3 VCMPNLE_UQSD reg1, reg2, reg3 VCMPORD_SSD | | VCMPSD reg1, reg2, reg3, 12H VCMPSD \n| reg1, reg2, reg3 VCMPEQ_USSD reg1, reg2, | | reg1, reg2, reg3, 13H VCMPSD reg1, reg2, \n| reg3 VCMPNGE_UQSD reg1, reg2, reg3 VCMPNGT_UQSD| | reg3, 14H VCMPSD reg1, reg2, reg3, 15H \n| reg1, reg2, reg3 VCMPFALSE_OSSD reg1, | | VCMPSD reg1, reg2, reg3, 16H VCMPSD \n| reg2, reg3 VCMPNEQ_OSSD reg1, reg2, | | reg1, reg2, reg3, 17H VCMPSD reg1, reg2, \n| reg3 VCMPGE_OQSD reg1, reg2, reg3 VCMPGT_OQSD | | reg3, 18H VCMPSD reg1, reg2, reg3, 19H \n| reg1, reg2, reg3 VCMPTRUE_USSD reg1, | | VCMPSD reg1, reg2, reg3, 1AH VCMPSD \n| reg2, reg3 | | reg1, reg2, reg3, 1BH VCMPSD reg1, reg2, \n| | | reg3, 1CH VCMPSD reg1, reg2, reg3, 1DH \n| | | VCMPSD reg1, reg2, reg3, 1EH VCMPSD \n| | | reg1, reg2, reg3, 1FH \nOperation:\n\nCASE (COMPARISON PREDICATE) OF\n 0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;\n 1: OP3 <- LT_OS; OP5 <- LT_OS;\n 2: OP3 <- LE_OS; OP5 <- LE_OS;\n 3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;\n 4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;\n 5: OP3 <- NLT_US; OP5 <- NLT_US;\n 6: OP3 <- NLE_US; OP5 <- NLE_US;\n 7: OP3 <- ORD_Q; OP5 <- ORD_Q;\n 8: OP5 <- EQ_UQ;\n 9: OP5 <- NGE_US;\n 10: OP5 <- NGT_US;\n 11: OP5 <- FALSE_OQ;\n 12: OP5 <- NEQ_OQ;\n 13: OP5 <- GE_OS;\n 14: OP5 <- GT_OS;\n 15: OP5 <- TRUE_UQ;\n 16: OP5 <- EQ_OS;\n 17: OP5 <- LT_OQ;\n 18: OP5 <- LE_OQ;\n 19: OP5 <- UNORD_S;\n 20: OP5 <- NEQ_US;\n 21: OP5 <- NLT_UQ;\n 22: OP5 <- NLE_UQ;\n 23: OP5 <- ORD_S;\n 24: OP5 <- EQ_US;\n 25: OP5 <- NGE_UQ;\n 26: OP5 <- NGT_UQ;\n 27: OP5 <- FALSE_OS;\n 28: OP5 <- NEQ_OS;\n 29: OP5 <- GE_OQ;\n 30: OP5 <- GT_OQ;\n 31: OP5 <- TRUE_US;\n DEFAULT: Reserved\nESAC;\nCMPSD (128-bit Legacy SSE version)\nCMP0 <- DEST[63:0] OP3 SRC[63:0];\nIF CMP0 = TRUE\nTHEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\nELSE DEST[63:0] <- 0000000000000000H; FI;\nDEST[VLMAX-1:64] (Unmodified)\nVCMPSD (VEX.128 encoded version)\nCMP0 <- SRC1[63:0] OP5 SRC2[63:0];\nIF CMP0 = TRUE\nTHEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\nELSE DEST[63:0] <- 0000000000000000H; FI;\nDEST[127:64] <- SRC1[127:64]\nDEST[VLMAX-1:128] <- 0\n\nIntel C/C++ Compiler Intrinsic Equivalents:\n| CMPSD for equality: | __m128d _mm_cmpeq_sd(__m128d a, __m128d \n| | b) \n| CMPSD for less-than: | __m128d _mm_cmplt_sd(__m128d a, __m128d \n| | b) \n| CMPSD for less-than-or-equal: | __m128d _mm_cmple_sd(__m128d a, __m128d \n| | b) \n| CMPSD for greater-than: | __m128d _mm_cmpgt_sd(__m128d a, __m128d \n| | b) \n| CMPSD for greater-than-or-equal: | __m128d _mm_cmpge_sd(__m128d a, __m128d \n| | b) \n| CMPSD for inequality: | __m128d _mm_cmpneq_sd(__m128d a, __m128d \n| | b) \n| CMPSD for not-less-than: | __m128d _mm_cmpnlt_sd(__m128d a, __m128d \n| | b) \n| CMPSD for not-greater-than: CMPSD for | __m128d _mm_cmpngt_sd(__m128d a, __m128d \n| not-greater-than-or-equal: __m128d _mm_cmpnge_sd(__m128d| b) \n| a, __m128d b) | \n| CMPSD for ordered: | __m128d _mm_cmpord_sd(__m128d a, __m128d \n| | b) \n| CMPSD for unordered: | __m128d _mm_cmpunord_sd(__m128d a, __m128d\n| | b) \n| CMPSD for not-less-than-or-equal: | __m128d _mm_cmpnle_sd(__m128d a, __m128d \n| | b) \n| VCMPSD: | __m128 _mm_cmp_sd(__m128 a, __m128 b, \n| | const int imm) \n\nSIMD Floating-Point Exceptions:\nInvalid if SNaN operand, Invalid if QNaN and predicate as listed in above table,\nDenormal.\n\n\nOther Exceptions:\nSee Exceptions Type 3. \n", "mnem": "CMPS" }, { @@ -240,10 +240,6 @@ "description": "-R:CMPS", "mnem": "CMPSD" }, - { - "description": "\nCMPSD - Compare Scalar Double-Precision Floating-Point Values:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, | RMI | V/V | SSE2 | Compare low double-precision floating-point\n| imm8 | | | | value in xmm2/m64 and xmm1 using imm8 \n| | | | | as comparison predicate. \n| VEX.NDS.LIG.F2.0F.WIG C2 /r ib VCMPSD| RVMI | V/V | AVX | Compare low double precision floating-point\n| xmm1, xmm2, xmm3/m64, imm8 | | | | value in xmm3/m64 and xmm2 using bits \n| | | | | 4:0 of imm8 as comparison predicate. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3 | Operand 4\n| RMI | ModRM:reg (r, w)| ModRM:r/m (r)| imm8 | NA \n| RVMI | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r)| imm8 \n\nDescription:\nCompares the low double-precision floating-point values in the source operand\n(second operand) and the destination operand (first operand) and returns the\nresults of the comparison to the destination operand. The comparison predicate\noperand (third operand) specifies the type of comparison performed. The comparison\nresult is a quadword mask of all 1s (comparison true) or all 0s (comparison\nfalse). The sign of zero is ignored for comparisons, so that -0.0 is equal to\n+0.0. 128-bit Legacy SSE version: The first source and destination operand (first\noperand) is an XMM register. The second source operand (second operand) can\nbe an XMM register or 64-bit memory location. The comparison predicate operand\nis an 8-bit immediate, bits 2:0 of the immediate define the type of comparison\nto be performed (see Table 3-7). Bits 7:3 of the immediate is reserved. Bits\n(VLMAX-1:64) of the corresponding YMM destination register remain unchanged.\n\nThe unordered relationship is true when at least one of the two source operands\nbeing compared is a NaN; the ordered relationship is true when neither source\noperand is a NaN.\n\nA subsequent computational instruction that uses the mask result in the destination\noperand as an input operand will not generate a fault, because a mask of all\n0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds\nto a QNaN.\n\nNote that processors with \u201cCPUID.1H:ECX.AVX =0\u201d do not implement the \u201cgreater-than\u201d,\n\u201cgreater-than-or-equal\u201d, \u201cnot-greater than\u201d, and \u201cnot-greater-than-or-equal\nrelations\u201d predicates. These comparisons can be made either by using the inverse\nrelationship (that is, use the \u201cnot-less-than-or-equal\u201d to make a \u201cgreater-than\u201d\ncomparison) or by using software emulation. When using software emulation, the\nprogram must swap the operands (copying registers when necessary to protect\nthe data that will now be in the destination operand), and then perform the\ncompare using a different predicate. The predicate to be used for these emulations\nis listed in Table 3-7 under the heading Emulation.\n\nCompilers and assemblers may implement the following two-operand pseudo-ops\nin addition to the three-operand CMPSD instruction, for processors with \u201cCPUID.1H:ECX.AVX\n=0\u201d. See Table 3-13. Compiler should treat reserved Imm8 values as illegal syntax.\n\n\nTable 3-13. Pseudo-Ops and CMPSD:\n| Pseudo-Op | Implementation \n| CMPEQSD xmm1, xmm2 | CMPSD xmm1,xmm2, 0\n| CMPLTSD xmm1, xmm2 | CMPSD xmm1,xmm2, 1\n| CMPLESD xmm1, xmm2 | CMPSD xmm1,xmm2, 2\n| CMPUNORDSD xmm1, xmm2| CMPSD xmm1,xmm2, 3\n| CMPNEQSD xmm1, xmm2 | CMPSD xmm1,xmm2, 4\n| CMPNLTSD xmm1, xmm2 | CMPSD xmm1,xmm2, 5\n| CMPNLESD xmm1, xmm2 | CMPSD xmm1,xmm2, 6\n| CMPORDSD xmm1, xmm2 | CMPSD xmm1,xmm2, 7\nThe greater-than relations not implemented in the processor require more than\none instruction to emulate in software and therefore should not be implemented\nas pseudo-ops. (For these, the programmer should reverse the operands of the\ncorresponding less than relations and use move instructions to ensure that the\nmask is moved to the correct destination register and that the source operand\nis left intact.)\n\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional\nregisters (XMM8-XMM15).\n\nEnhanced Comparison Predicate for VEX-Encoded VCMPSD VEX.128 encoded version:\nThe first source operand (second operand) is an XMM register. The second source\noperand (third operand) can be an XMM register or a 64-bit memory location.\nBits (VLMAX-1:128) of the destination YMM register are zeroed. The comparison\npredicate operand is an 8-bit immediate:\n\n - For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison\nto be performed (see Table 3-9). Bits 5 through 7 of the immediate are reserved.\n\nProcessors with \u201cCPUID.1H:ECX.AVX =1\u201d implement the full complement of 32 predicates\nshown in Table 3-9, software emulation is no longer needed. Compilers and assemblers\nmay implement the following three-operand pseudo-ops in addition to the four-operand\nVCMPSD instruction. See Table 3-14, where the notations of reg1 reg2, and reg3\nrepresent either XMM registers or YMM registers. Compiler should treat reserved\nImm8 values as illegal syntax. Alternately, intrinsics can map the pseudo-ops\nto pre-defined constants to support a simpler intrinsic interface.\n\n| : Pseudo-Op VCMPEQSD reg1, reg2, reg3 | Table 3-14. Table 3-14.| Pseudo-Op and VCMPSD Implementation \n| VCMPLTSD reg1, reg2, reg3 VCMPLESD reg1, | | CMPSD Implementation VCMPSD reg1, reg2, \n| reg2, reg3 VCMPUNORDSD reg1, reg2, reg3 | | reg3, 0 VCMPSD reg1, reg2, reg3, 1 VCMPSD\n| VCMPNEQSD reg1, reg2, reg3 VCMPNLTSD | | reg1, reg2, reg3, 2 VCMPSD reg1, reg2, \n| reg1, reg2, reg3 VCMPNLESD reg1, reg2, | | reg3, 3 VCMPSD reg1, reg2, reg3, 4 VCMPSD\n| reg3 VCMPORDSD reg1, reg2, reg3 VCMPEQ_UQSD | | reg1, reg2, reg3, 5 VCMPSD reg1, reg2, \n| reg1, reg2, reg3 VCMPNGESD reg1, reg2, | | reg3, 6 VCMPSD reg1, reg2, reg3, 7 VCMPSD\n| reg3 VCMPNGTSD reg1, reg2, reg3 VCMPFALSESD | | reg1, reg2, reg3, 8 VCMPSD reg1, reg2, \n| reg1, reg2, reg3 VCMPNEQ_OQSD reg1, | | reg3, 9 VCMPSD reg1, reg2, reg3, 0AH \n| reg2, reg3 VCMPGESD reg1, reg2, reg3 | | VCMPSD reg1, reg2, reg3, 0BH VCMPSD \n| VCMPGTSD reg1, reg2, reg3 Pseudo-Op | | reg1, reg2, reg3, 0CH VCMPSD reg1, reg2, \n| VCMPTRUESD reg1, reg2, reg3 VCMPEQ_OSSD | | reg3, 0DH VCMPSD reg1, reg2, reg3, 0EH \n| reg1, reg2, reg3 VCMPLT_OQSD reg1, reg2, | | Pseudo-Op and VCMPSD Implementation \n| reg3 VCMPLE_OQSD reg1, reg2, reg3 VCMPUNORD_SSD| | (Contd.) CMPSD Implementation VCMPSD \n| reg1, reg2, reg3 VCMPNEQ_USSD reg1, | | reg1, reg2, reg3, 0FH VCMPSD reg1, reg2, \n| reg2, reg3 VCMPNLT_UQSD reg1, reg2, | | reg3, 10H VCMPSD reg1, reg2, reg3, 11H \n| reg3 VCMPNLE_UQSD reg1, reg2, reg3 VCMPORD_SSD | | VCMPSD reg1, reg2, reg3, 12H VCMPSD \n| reg1, reg2, reg3 VCMPEQ_USSD reg1, reg2, | | reg1, reg2, reg3, 13H VCMPSD reg1, reg2, \n| reg3 VCMPNGE_UQSD reg1, reg2, reg3 VCMPNGT_UQSD| | reg3, 14H VCMPSD reg1, reg2, reg3, 15H \n| reg1, reg2, reg3 VCMPFALSE_OSSD reg1, | | VCMPSD reg1, reg2, reg3, 16H VCMPSD \n| reg2, reg3 VCMPNEQ_OSSD reg1, reg2, | | reg1, reg2, reg3, 17H VCMPSD reg1, reg2, \n| reg3 VCMPGE_OQSD reg1, reg2, reg3 VCMPGT_OQSD | | reg3, 18H VCMPSD reg1, reg2, reg3, 19H \n| reg1, reg2, reg3 VCMPTRUE_USSD reg1, | | VCMPSD reg1, reg2, reg3, 1AH VCMPSD \n| reg2, reg3 | | reg1, reg2, reg3, 1BH VCMPSD reg1, reg2, \n| | | reg3, 1CH VCMPSD reg1, reg2, reg3, 1DH \n| | | VCMPSD reg1, reg2, reg3, 1EH VCMPSD \n| | | reg1, reg2, reg3, 1FH \nOperation:\n\nCASE (COMPARISON PREDICATE) OF\n 0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;\n 1: OP3 <- LT_OS; OP5 <- LT_OS;\n 2: OP3 <- LE_OS; OP5 <- LE_OS;\n 3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;\n 4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;\n 5: OP3 <- NLT_US; OP5 <- NLT_US;\n 6: OP3 <- NLE_US; OP5 <- NLE_US;\n 7: OP3 <- ORD_Q; OP5 <- ORD_Q;\n 8: OP5 <- EQ_UQ;\n 9: OP5 <- NGE_US;\n 10: OP5 <- NGT_US;\n 11: OP5 <- FALSE_OQ;\n 12: OP5 <- NEQ_OQ;\n 13: OP5 <- GE_OS;\n 14: OP5 <- GT_OS;\n 15: OP5 <- TRUE_UQ;\n 16: OP5 <- EQ_OS;\n 17: OP5 <- LT_OQ;\n 18: OP5 <- LE_OQ;\n 19: OP5 <- UNORD_S;\n 20: OP5 <- NEQ_US;\n 21: OP5 <- NLT_UQ;\n 22: OP5 <- NLE_UQ;\n 23: OP5 <- ORD_S;\n 24: OP5 <- EQ_US;\n 25: OP5 <- NGE_UQ;\n 26: OP5 <- NGT_UQ;\n 27: OP5 <- FALSE_OS;\n 28: OP5 <- NEQ_OS;\n 29: OP5 <- GE_OQ;\n 30: OP5 <- GT_OQ;\n 31: OP5 <- TRUE_US;\n DEFAULT: Reserved\nESAC;\nCMPSD (128-bit Legacy SSE version)\nCMP0 <- DEST[63:0] OP3 SRC[63:0];\nIF CMP0 = TRUE\nTHEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\nELSE DEST[63:0] <- 0000000000000000H; FI;\nDEST[VLMAX-1:64] (Unmodified)\nVCMPSD (VEX.128 encoded version)\nCMP0 <- SRC1[63:0] OP5 SRC2[63:0];\nIF CMP0 = TRUE\nTHEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\nELSE DEST[63:0] <- 0000000000000000H; FI;\nDEST[127:64] <- SRC1[127:64]\nDEST[VLMAX-1:128] <- 0\n\nIntel C/C++ Compiler Intrinsic Equivalents:\n| CMPSD for equality: | __m128d _mm_cmpeq_sd(__m128d a, __m128d \n| | b) \n| CMPSD for less-than: | __m128d _mm_cmplt_sd(__m128d a, __m128d \n| | b) \n| CMPSD for less-than-or-equal: | __m128d _mm_cmple_sd(__m128d a, __m128d \n| | b) \n| CMPSD for greater-than: | __m128d _mm_cmpgt_sd(__m128d a, __m128d \n| | b) \n| CMPSD for greater-than-or-equal: | __m128d _mm_cmpge_sd(__m128d a, __m128d \n| | b) \n| CMPSD for inequality: | __m128d _mm_cmpneq_sd(__m128d a, __m128d \n| | b) \n| CMPSD for not-less-than: | __m128d _mm_cmpnlt_sd(__m128d a, __m128d \n| | b) \n| CMPSD for not-greater-than: CMPSD for | __m128d _mm_cmpngt_sd(__m128d a, __m128d \n| not-greater-than-or-equal: __m128d _mm_cmpnge_sd(__m128d| b) \n| a, __m128d b) | \n| CMPSD for ordered: | __m128d _mm_cmpord_sd(__m128d a, __m128d \n| | b) \n| CMPSD for unordered: | __m128d _mm_cmpunord_sd(__m128d a, __m128d\n| | b) \n| CMPSD for not-less-than-or-equal: | __m128d _mm_cmpnle_sd(__m128d a, __m128d \n| | b) \n| VCMPSD: | __m128 _mm_cmp_sd(__m128 a, __m128 b, \n| | const int imm) \n\nSIMD Floating-Point Exceptions:\nInvalid if SNaN operand, Invalid if QNaN and predicate as listed in above table,\nDenormal.\n\n\nOther Exceptions:\nSee Exceptions Type 3.\n\n", - "mnem": "CMPSD" - }, { "description": "-R:CMPS", "mnem": "CMPSQ" @@ -1041,15 +1037,7 @@ "mnem": "MONITOR" }, { - "description": "\nMOV - Move:\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| 88 /r REX + 88 /r | MOV r/m8,r8 MOV r/m8***,r8*** | MR MR| Valid Valid| Valid N.E. | Move r8 to r/m8. Move r8 to r/m8. \n| 89 /r | MOV r/m16,r16 | MR | Valid | Valid | Move r16 to r/m16. \n| 89 /r | MOV r/m32,r32 | MR | Valid | Valid | Move r32 to r/m32. \n| REX.W + 89 /r | MOV r/m64,r64 | MR | Valid | N.E. | Move r64 to r/m64. \n| 8A /r | MOV r8,r/m8 | RM | Valid | Valid | Move r/m8 to r8. \n| REX + 8A /r | MOV r8***,r/m8*** | RM | Valid | N.E. | Move r/m8 to r8. \n| 8B /r | MOV r16,r/m16 | RM | Valid | Valid | Move r/m16 to r16. \n| 8B /r | MOV r32,r/m32 | RM | Valid | Valid | Move r/m32 to r32. \n| REX.W + 8B /r | MOV r64,r/m64 | RM | Valid | N.E. | Move r/m64 to r64. \n| 8C /r | MOV r/m16,Sreg** | MR | Valid | Valid | Move segment register to r/m16. \n| REX.W + 8C /r | MOV r/m64,Sreg** | MR | Valid | Valid | Move zero extended 16-bit segment register\n| | | | | | to r/m64. \n| 8E /r | MOV Sreg,r/m16** | RM | Valid | Valid | Move r/m16 to segment register. \n| REX.W + 8E /r | MOV Sreg,r/m64** | RM | Valid | Valid | Move lower 16 bits of r/m64 to segment \n| | | | | | register. \n| A0 | MOV AL,moffs8* | FD | Valid | Valid | Move byte at (seg:offset) to AL. \n| REX.W + A0 | MOV AL,moffs8* | FD | Valid | N.E. | Move byte at (offset) to AL. \n| A1 | MOV AX,moffs16* | FD | Valid | Valid | Move word at (seg:offset) to AX. \n| A1 | MOV EAX,moffs32* | FD | Valid | Valid | Move doubleword at (seg:offset) to EAX. \n| REX.W + A1 | MOV RAX,moffs64* | FD | Valid | N.E. | Move quadword at (offset) to RAX. \n| A2 REX.W + A2 | MOV moffs8,AL MOV moffs8***,AL| TD TD| Valid Valid| Valid N.E. | Move AL to (seg:offset). Move AL to \n| | | | | | (offset). \n| A3 | MOV moffs16*,AX | TD | Valid | Valid | Move AX to (seg:offset). \n| A3 | MOV moffs32*,EAX | TD | Valid | Valid | Move EAX to (seg:offset). \n| REX.W + A3 | MOV moffs64*,RAX | TD | Valid | N.E. | Move RAX to (offset). \n| B0+ rb ib REX + B0+ rb ib| MOV r8, imm8 MOV r8***, imm8 | OI OI| Valid Valid| Valid N.E. | Move imm8 to r8. Move imm8 to r8. \n| B8+ rw iw | MOV r16, imm16 | OI | Valid | Valid | Move imm16 to r16. \n| B8+ rd id | MOV r32, imm32 | OI | Valid | Valid | Move imm32 to r32. \n| REX.W + B8+ rd io | MOV r64, imm64 | OI | Valid | N.E. | Move imm64 to r64. \n| C6 /0 ib | MOV r/m8, imm8 | MI | Valid | Valid | Move imm8 to r/m8. \n| REX + C6 /0 ib | MOV r/m8***, imm8 | MI | Valid | N.E. | Move imm8 to r/m8. \n| C7 /0 iw | MOV r/m16, imm16 | MI | Valid | Valid | Move imm16 to r/m16. \n| C7 /0 id | MOV r/m32, imm32 | MI | Valid | Valid | Move imm32 to r/m32. \n| REX.W + C7 /0 io | MOV r/m64, imm32 | MI | Valid | N.E. | Move imm32 sign extended to 64-bits \n| | | | | | to r/m64. \nNotes: * The moffs8, moffs16, moffs32 and moffs64 operands specify a simple\noffset relative to the segment base, where 8, 16, 32 and 64 refer to the size\nof the data. The address-size attribute of the instruction determines the size\nof the offset, either 16, 32 or 64 bits. ** In 32-bit mode, the assembler may\ninsert the 16-bit operand-size prefix with this instruction (see the following\n\u201cDescription\u201d section for further information). ***In 64-bit mode, r/m8 can\nnot be encoded to access the following byte registers if a REX prefix is used:\nAH, BH, CH, DH.\n\n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| MR | ModRM:r/m (w) | ModRM:reg (r)| NA | NA \n| RM | ModRM:reg (w) | ModRM:r/m (r)| NA | NA \n| FD | AL/AX/EAX/RAX | Moffs | NA | NA \n| TD | Moffs (w) | AL/AX/EAX/RAX| NA | NA \n| OI | opcode + rd (w)| imm8/16/32/64| NA | NA \n| MI | ModRM:r/m (w) | imm8/16/32/64| NA | NA \n\nDescription:\nCopies the second operand (source operand) to the first operand (destination\noperand). The source operand can be an immediate value, general-purpose register,\nsegment register, or memory location; the destination register can be a general-purpose\nregister, segment register, or memory location. Both operands must be the same\nsize, which can be a byte, a word, a doubleword, or a quadword.\n\nThe MOV instruction cannot be used to load the CS register. Attempting to do\nso results in an invalid opcode exception (#UD). To load the CS register, use\nthe far JMP, CALL, or RET instruction.\n\nIf the destination operand is a segment register (DS, ES, FS, GS, or SS), the\nsource operand must be a valid segment selector. In protected mode, moving a\nsegment selector into a segment register automatically causes the segment descriptor\ninformation associated with that segment selector to be loaded into the hidden\n(shadow) part of the segment register. While loading this information, the segment\nselector and segment descriptor information is validated (see the \u201cOperation\u201d\nalgorithm below). The segment descriptor data is obtained from the GDT or LDT\nentry for the specified segment selector.\n\nA NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS,\nand GS registers without causing a protection exception. However, any subsequent\nattempt to reference a segment whose corresponding segment register is loaded\nwith a NULL value causes a general protection exception (#GP) and no memory\nreference occurs.\n\nLoading the SS register with a MOV instruction inhibits all interrupts until\nafter the execution of the next instruction. This operation allows a stack pointer\nto be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer\nvalue) before an interrupt occurs1. Be aware that the LSS instruction offers\na more efficient method of loading the SS and ESP registers.\n\nWhen operating in 32-bit mode and moving data between a segment register and\na general-purpose register, the 32-bit IA-32 processors do not require the use\nof the 16-bit operand-size prefix (a byte with the value 66H) with\n\n| 1.| If a code instruction breakpoint (for \n| | debug) is placed on an instruction located \n| | immediately after a MOV SS instruction, \n| | the breakpoint may not be triggered. \n| | However, in a sequence of instructions \n| | that load the SS register, only the \n| | first instruction in the sequence is \n| | guaranteed to delay an interrupt. In \n| | the following sequence, interrupts may \n| | be recognized before MOV ESP, EBP executes:\n| | MOV SS, EDX MOV SS, EAX MOV ESP, EBP \nthis instruction, but most assemblers will insert it if the standard form of\nthe instruction is used (for example, MOV DS, AX). The processor will execute\nthis instruction correctly, but it will usually require an extra clock. With\nmost assemblers, using the instruction form MOV DS, EAX will avoid this unneeded\n66H prefix. When the processor executes the instruction with a 32-bit general-purpose\nregister, it assumes that the 16 least-significant bits of the general-purpose\nregister are the destination or source operand. If the register is a destination\noperand, the resulting value in the two high-order bytes of the register is\nimplementation dependent. For the Pentium 4, Intel Xeon, and P6 family processors,\nthe two high-order bytes are filled with zeros; for earlier 32-bit IA-32 processors,\nthe two high order bytes are undefined.\n\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of\nthe REX.R prefix permits access to additional registers (R8-R15). Use of the\nREX.W prefix promotes operation to 64 bits. See the summary chart at the beginning\nof this section for encoding data and limits.\n\nOperation:\n\nDEST <- SRC;\nLoading a segment register while in protected mode results in special checks and actions, as described in the\nfollowing listing. These checks are performed on the segment selector and the segment descriptor to which it\npoints.\nIF SS is loaded\n THEN\n IF segment selector is NULL\n THEN #GP(0); FI;\n IF segment selector index is outside descriptor table limits\n or segment selector's RPL != CPL\n or segment is not a writable data segment\n or DPL != CPL\n THEN #GP(selector); FI;\n IF segment not marked present\n THEN #SS(selector);\n ELSE\n SS <- segment selector;\n SS <- segment descriptor; FI;\nFI;\nIF DS, ES, FS, or GS is loaded with non-NULL selector\nTHEN\n IF segment selector index is outside descriptor table limits\n or segment is not a data or readable code segment\n or ((segment is a data or nonconforming code segment)\n or ((RPL > DPL) and (CPL > DPL))\n THEN #GP(selector); FI;\n IF segment not marked present\n THEN #NP(selector);\n ELSE\n SegmentRegister <- segment selector;\n SegmentRegister <- segment descriptor; FI;\nFI;\nIF DS, ES, FS, or GS is loaded with NULL selector\n THEN\n SegmentRegister <- segment selector;\n SegmentRegister <- segment descriptor;\nFI;\n\nFlags Affected:\nNone.\n\n\nProtected Mode Exceptions:\n| #GP(0) | If attempt is made to load SS register \n| | with NULL segment selector. If the destination\n| | operand is in a non-writable segment. \n| | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. If the DS, ES, FS, or \n| | GS register contains a NULL segment \n| | selector. \n| #GP(selector) | If segment selector index is outside \n| | descriptor table limits. If the SS register \n| | is being loaded and the segment selector's \n| | RPL and the segment descriptor's DPL \n| | are not equal to the CPL. If the SS \n| | register is being loaded and the segment \n| | pointed to is a non-writable data segment. \n| | If the DS, ES, FS, or GS register is \n| | being loaded and the segment pointed \n| | to is not a data or readable code segment. \n| | If the DS, ES, FS, or GS register is \n| | being loaded and the segment pointed \n| | to is a data or nonconforming code segment, \n| | but both the RPL and the CPL are greater \n| | than the DPL. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #SS(selector) | If the SS register is being loaded and \n| | the segment pointed to is marked not \n| | present. \n| #NP | If the DS, ES, FS, or GS register is \n| | being loaded and the segment pointed \n| | to is marked not present. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If attempt is made to load the CS register. \n| | If the LOCK prefix is used. \n\nReal-Address Mode Exceptions:\n| #GP| If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS| If a memory operand effective address \n| | is outside the SS segment limit. \n| #UD| If attempt is made to load the CS register.\n| | If the LOCK prefix is used. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0) | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made. \n| #UD | If attempt is made to load the CS register.\n| | If the LOCK prefix is used. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #GP(0) | If the memory address is in a non-canonical \n| | form. If an attempt is made to load \n| | SS register with NULL segment selector \n| | when CPL = 3. If an attempt is made \n| | to load SS register with NULL segment \n| | selector when CPL < 3 and CPL != RPL. \n| #GP(selector) | If segment selector index is outside \n| | descriptor table limits. If the memory \n| | access to the descriptor table is non-canonical.\n| | If the SS register is being loaded and \n| | the segment selector's RPL and the segment \n| | descriptor's DPL are not equal to the \n| | CPL. If the SS register is being loaded \n| | and the segment pointed to is a nonwritable \n| | data segment. If the DS, ES, FS, or \n| | GS register is being loaded and the \n| | segment pointed to is not a data or \n| | readable code segment. If the DS, ES, \n| | FS, or GS register is being loaded and \n| | the segment pointed to is a data or \n| | nonconforming code segment, but both \n| | the RPL and the CPL are greater than \n| | the DPL. \n| #SS(0) | If the stack address is in a non-canonical \n| | form. \n| #SS(selector) | If the SS register is being loaded and \n| | the segment pointed to is marked not \n| | present. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If attempt is made to load the CS register. \n| | If the LOCK prefix is used. \n", - "mnem": "MOV" - }, - { - "description": "\nMOV - Move to/from Control Registers:\n| Opcode/Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| 0F 20/r MOV r32, CR0-CR7 | MR | N.E. | Valid | Move control register to r32. \n| 0F 20/r MOV r64, CR0-CR7 REX.R + 0F| MR MR| Valid Valid| N.E. N.E. | Move extended control register to r64.\n| 20 /0 MOV r64, CR8 | | | | Move extended CR8 to r64.1 \n| 0F 22 /r MOV CR0-CR7, r32 | RM | N.E. | Valid | Move r32 to control register. \n| 0F 22 /r MOV CR0-CR7, r64 | RM | Valid | N.E. | Move r64 to extended control register.\n| REX.R + 0F 22 /0 MOV CR8, r64 | RM | Valid | N.E. | Move r64 to extended CR8.1 \n\nNOTE::\n| 1.| MOV CR* instructions, except for MOV \n| | CR8, are serializing instructions. MOV\n| | CR8 is not architecturally defined as \n| | a serializing instruction. For more \n| | information, see Chapter 8 in Intel\u00ae \n| | 64 and IA-32 Architectures Software \n| | Developer's Manual, Volume 3A. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n\nDescription:\nMoves the contents of a control register (CR0, CR2, CR3, CR4, or CR8) to a general-purpose\nregister or the contents of a general purpose register to a control register.\nThe operand size for these instructions is always 32 bits in non-64-bit modes,\nregardless of the operand-size attribute. (See \u201cControl Registers\u201d in Chapter\n2 of the Intel\u00ae64 and IA-32 Architectures Software Developer's Manual, Volume\n3A, for a detailed description of the flags and fields in the control registers.)\nThis instruction can be executed only when the current privilege level is 0.\n\nAt the opcode level, the reg field within the ModR/M byte specifies which of\nthe control registers is loaded or read. The 2 bits in the mod field are ignored.\nThe r/m field specifies the general-purpose register loaded or read. Attempts\nto reference CR1, CR5, CR6, CR7, and CR9-CR15 result in undefined opcode (#UD)\nexceptions.\n\nWhen loading control registers, programs should not attempt to change the reserved\nbits; that is, always set reserved bits to the value previously read. An attempt\nto change CR4's reserved bits will cause a general protection fault. Reserved\nbits in CR0 and CR3 remain clear after any load of those registers; attempts\nto set them have no impact. On Pentium 4, Intel Xeon and P6 family processors,\nCR0.ET remains set after any load of CR0; attempts to clear this bit have no\nimpact.\n\nIn certain cases, these instructions have the side effect of invalidating entries\nin the TLBs and the paging-structure caches. See Section 4.10.4.1, \u201cOperations\nthat Invalidate TLBs and Paging-Structure Caches,\u201d in the Intel\u00ae 64 and IA-32\nArchitectures Software Developer's Manual, Volume 3A for details.\n\nThe following side effects are implementation-specific for the Pentium 4, Intel\nXeon, and P6 processor family: when modifying PE or PG in register CR0, or PSE\nor PAE in register CR4, all TLB entries are flushed, including global entries.\nSoftware should not depend on this functionality in all Intel 64 or IA-32 processors.\n\nIn 64-bit mode, the instruction's default operation size is 64 bits. The REX.R\nprefix must be used to access CR8. Use of REX.B permits access to additional\nregisters (R8-R15). Use of the REX.W prefix or 66H prefix is ignored. Use of\n\nthe REX.R prefix to specify a register other than CR8 causes an invalid-opcode\nexception. See the summary chart at the beginning of this section for encoding\ndata and limits.\n\nIf CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether\nthe instruction invalidates entries in the TLBs and the paging-structure caches\n(see Section 4.10.4.1, \u201cOperations that Invalidate TLBs and Paging-Structure\nCaches,\u201d in the Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual,\nVolume 3A). The instruction does not modify bit 63 of CR3, which is reserved\nand always 0.\n\nSee \u201cChanges to Instruction Behavior in VMX Non-Root Operation\u201d in Chapter 25\nof the Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual, Volume\n3C, for more information about the behavior of this instruction in VMX non-root\noperation.\n\nOperation:\n\nDEST <- SRC;\n\nFlags Affected:\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\n\n\nProtected Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write invalid\n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0, or setting the CD flag to \n| | 0 when the NW flag is set to 1). If \n| | an attempt is made to write a 1 to any \n| | reserved bit in CR4. If an attempt is \n| | made to write 1 to CR4.PCIDE. If any \n| | of the reserved bits are set in the \n| | page-directory pointers table (PDPT) \n| | and the loading of a control register \n| | causes the PDPT to be loaded into the \n| | processor. \n| #UD | If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. \n\nReal-Address Mode Exceptions:\n| #GP| If an attempt is made to write a 1 to \n| | any reserved bit in CR4. If an attempt \n| | is made to write 1 to CR4.PCIDE. If \n| | an attempt is made to write invalid \n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0). \n| #UD| If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0)| These instructions cannot be executed\n| | in virtual-8086 mode. \n\nCompatibility Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write invalid\n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0, or setting the CD flag to \n| | 0 when the NW flag is set to 1). If \n| | an attempt is made to change CR4.PCIDE \n| | from 0 to 1 while CR3[11:0] != 000H. \n| | If an attempt is made to clear CR0.PG[bit\n| | 31] while CR4.PCIDE = 1. If an attempt \n| | is made to write a 1 to any reserved \n| | bit in CR3. If an attempt is made to \n| | leave IA-32e mode by clearing CR4.PAE[bit\n| | 5]. \n| #UD | If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. \n\n64-Bit Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write invalid\n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0, or setting the CD flag to \n| | 0 when the NW flag is set to 1). If \n| | an attempt is made to change CR4.PCIDE \n| | from 0 to 1 while CR3[11:0] != 000H. \n| | If an attempt is made to clear CR0.PG[bit\n| | 31]. If an attempt is made to write \n| | a 1 to any reserved bit in CR4. If an \n| | attempt is made to write a 1 to any \n| | reserved bit in CR8. If an attempt is \n| | made to write a 1 to any reserved bit \n| | in CR3. If an attempt is made to leave \n| | IA-32e mode by clearing CR4.PAE[bit \n| | 5]. \n| #UD | If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. If the REX.R prefix is used to \n| | specify a register other than CR8. \n", - "mnem": "MOV" - }, - { - "description": "\nMOV - Move to/from Debug Registers:\n| Opcode/Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| 0F 21/r MOV r32, DR0-DR7 | MR | N.E. | Valid | Move debug register to r32. \n| 0F 21/r MOV r64, DR0-DR7 | MR | Valid | N.E. | Move extended debug register to r64.\n| 0F 23 /r MOV DR0-DR7, r32| RM | N.E. | Valid | Move r32 to debug register. \n| 0F 23 /r MOV DR0-DR7, r64| RM | Valid | N.E. | Move r64 to extended debug register.\n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n\nDescription:\nMoves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or\nDR7) to a general-purpose register or vice versa. The operand size for these\ninstructions is always 32 bits in non-64-bit modes, regardless of the operand-size\nattribute. (See Section 17.2, \u201cDebug Registers\u201d, of the Intel\u00ae 64 and IA-32\nArchitectures Software Developer's Manual, Volume 3A, for a detailed description\nof the flags and fields in the debug registers.)\n\nThe instructions must be executed at privilege level 0 or in real-address mode.\n\nWhen the debug extension (DE) flag in register CR4 is clear, these instructions\noperate on debug registers in a manner that is compatible with Intel386 and\nIntel486 processors. In this mode, references to DR4 and DR5 refer to DR6 and\nDR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4\nand DR5 result in an undefined opcode (#UD) exception. (The CR4 register was\nadded to the IA-32 Architecture beginning with the Pentium processor.)\n\nAt the opcode level, the reg field within the ModR/M byte specifies which of\nthe debug registers is loaded or read. The two bits in the mod field are ignored.\nThe r/m field specifies the general-purpose register loaded or read.\n\nIn 64-bit mode, the instruction's default operation size is 64 bits. Use of\nthe REX.B prefix permits access to additional registers (R8-R15). Use of the\nREX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalidopcode\nexception. See the summary chart at the beginning of this section for encoding\ndata and limits.\n\nOperation:\n\nIF ((DE = 1) and (SRC or DEST = DR4 or DR5))\n THEN\n #UD;\n ELSE\n DEST <- SRC;\nFI;\n\nFlags Affected:\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\n\n\nProtected Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. \n| #UD | If CR4.DE[bit 3] = 1 (debug extensions) \n| | and a MOV instruction is executed involving\n| | DR4 or DR5. If the LOCK prefix is used. \n| #DB | If any debug register is accessed while \n| | the DR7.GD[bit 13] = 1. \n\nReal-Address Mode Exceptions:\n| #UD| If CR4.DE[bit 3] = 1 (debug extensions) \n| | and a MOV instruction is executed involving\n| | DR4 or DR5. If the LOCK prefix is used. \n| #DB| If any debug register is accessed while \n| | the DR7.GD[bit 13] = 1. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0)| The debug registers cannot be loaded\n| | or read when in virtual-8086 mode. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write a \n| | 1 to any of bits 63:32 in DR6. If an \n| | attempt is made to write a 1 to any \n| | of bits 63:32 in DR7. \n| #UD | If CR4.DE[bit 3] = 1 (debug extensions) \n| | and a MOV instruction is executed involving\n| | DR4 or DR5. If the LOCK prefix is used. \n| | If the REX.R prefix is used. \n| #DB | If any debug register is accessed while \n| | the DR7.GD[bit 13] = 1. \n", + "description": "\nMOV - Move:\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| 88 /r REX + 88 /r | MOV r/m8,r8 MOV r/m8***,r8*** | MR MR| Valid Valid| Valid N.E. | Move r8 to r/m8. Move r8 to r/m8. \n| 89 /r | MOV r/m16,r16 | MR | Valid | Valid | Move r16 to r/m16. \n| 89 /r | MOV r/m32,r32 | MR | Valid | Valid | Move r32 to r/m32. \n| REX.W + 89 /r | MOV r/m64,r64 | MR | Valid | N.E. | Move r64 to r/m64. \n| 8A /r | MOV r8,r/m8 | RM | Valid | Valid | Move r/m8 to r8. \n| REX + 8A /r | MOV r8***,r/m8*** | RM | Valid | N.E. | Move r/m8 to r8. \n| 8B /r | MOV r16,r/m16 | RM | Valid | Valid | Move r/m16 to r16. \n| 8B /r | MOV r32,r/m32 | RM | Valid | Valid | Move r/m32 to r32. \n| REX.W + 8B /r | MOV r64,r/m64 | RM | Valid | N.E. | Move r/m64 to r64. \n| 8C /r | MOV r/m16,Sreg** | MR | Valid | Valid | Move segment register to r/m16. \n| REX.W + 8C /r | MOV r/m64,Sreg** | MR | Valid | Valid | Move zero extended 16-bit segment register\n| | | | | | to r/m64. \n| 8E /r | MOV Sreg,r/m16** | RM | Valid | Valid | Move r/m16 to segment register. \n| REX.W + 8E /r | MOV Sreg,r/m64** | RM | Valid | Valid | Move lower 16 bits of r/m64 to segment \n| | | | | | register. \n| A0 | MOV AL,moffs8* | FD | Valid | Valid | Move byte at (seg:offset) to AL. \n| REX.W + A0 | MOV AL,moffs8* | FD | Valid | N.E. | Move byte at (offset) to AL. \n| A1 | MOV AX,moffs16* | FD | Valid | Valid | Move word at (seg:offset) to AX. \n| A1 | MOV EAX,moffs32* | FD | Valid | Valid | Move doubleword at (seg:offset) to EAX. \n| REX.W + A1 | MOV RAX,moffs64* | FD | Valid | N.E. | Move quadword at (offset) to RAX. \n| A2 REX.W + A2 | MOV moffs8,AL MOV moffs8***,AL| TD TD| Valid Valid| Valid N.E. | Move AL to (seg:offset). Move AL to \n| | | | | | (offset). \n| A3 | MOV moffs16*,AX | TD | Valid | Valid | Move AX to (seg:offset). \n| A3 | MOV moffs32*,EAX | TD | Valid | Valid | Move EAX to (seg:offset). \n| REX.W + A3 | MOV moffs64*,RAX | TD | Valid | N.E. | Move RAX to (offset). \n| B0+ rb ib REX + B0+ rb ib| MOV r8, imm8 MOV r8***, imm8 | OI OI| Valid Valid| Valid N.E. | Move imm8 to r8. Move imm8 to r8. \n| B8+ rw iw | MOV r16, imm16 | OI | Valid | Valid | Move imm16 to r16. \n| B8+ rd id | MOV r32, imm32 | OI | Valid | Valid | Move imm32 to r32. \n| REX.W + B8+ rd io | MOV r64, imm64 | OI | Valid | N.E. | Move imm64 to r64. \n| C6 /0 ib | MOV r/m8, imm8 | MI | Valid | Valid | Move imm8 to r/m8. \n| REX + C6 /0 ib | MOV r/m8***, imm8 | MI | Valid | N.E. | Move imm8 to r/m8. \n| C7 /0 iw | MOV r/m16, imm16 | MI | Valid | Valid | Move imm16 to r/m16. \n| C7 /0 id | MOV r/m32, imm32 | MI | Valid | Valid | Move imm32 to r/m32. \n| REX.W + C7 /0 io | MOV r/m64, imm32 | MI | Valid | N.E. | Move imm32 sign extended to 64-bits \n| | | | | | to r/m64. \nNotes: * The moffs8, moffs16, moffs32 and moffs64 operands specify a simple\noffset relative to the segment base, where 8, 16, 32 and 64 refer to the size\nof the data. The address-size attribute of the instruction determines the size\nof the offset, either 16, 32 or 64 bits. ** In 32-bit mode, the assembler may\ninsert the 16-bit operand-size prefix with this instruction (see the following\n\u201cDescription\u201d section for further information). ***In 64-bit mode, r/m8 can\nnot be encoded to access the following byte registers if a REX prefix is used:\nAH, BH, CH, DH.\n\n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| MR | ModRM:r/m (w) | ModRM:reg (r)| NA | NA \n| RM | ModRM:reg (w) | ModRM:r/m (r)| NA | NA \n| FD | AL/AX/EAX/RAX | Moffs | NA | NA \n| TD | Moffs (w) | AL/AX/EAX/RAX| NA | NA \n| OI | opcode + rd (w)| imm8/16/32/64| NA | NA \n| MI | ModRM:r/m (w) | imm8/16/32/64| NA | NA \n\nDescription:\nCopies the second operand (source operand) to the first operand (destination\noperand). The source operand can be an immediate value, general-purpose register,\nsegment register, or memory location; the destination register can be a general-purpose\nregister, segment register, or memory location. Both operands must be the same\nsize, which can be a byte, a word, a doubleword, or a quadword.\n\nThe MOV instruction cannot be used to load the CS register. Attempting to do\nso results in an invalid opcode exception (#UD). To load the CS register, use\nthe far JMP, CALL, or RET instruction.\n\nIf the destination operand is a segment register (DS, ES, FS, GS, or SS), the\nsource operand must be a valid segment selector. In protected mode, moving a\nsegment selector into a segment register automatically causes the segment descriptor\ninformation associated with that segment selector to be loaded into the hidden\n(shadow) part of the segment register. While loading this information, the segment\nselector and segment descriptor information is validated (see the \u201cOperation\u201d\nalgorithm below). The segment descriptor data is obtained from the GDT or LDT\nentry for the specified segment selector.\n\nA NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS,\nand GS registers without causing a protection exception. However, any subsequent\nattempt to reference a segment whose corresponding segment register is loaded\nwith a NULL value causes a general protection exception (#GP) and no memory\nreference occurs.\n\nLoading the SS register with a MOV instruction inhibits all interrupts until\nafter the execution of the next instruction. This operation allows a stack pointer\nto be loaded into the ESP register with the next instruction (MOV ESP, stack-pointer\nvalue) before an interrupt occurs1. Be aware that the LSS instruction offers\na more efficient method of loading the SS and ESP registers.\n\nWhen operating in 32-bit mode and moving data between a segment register and\na general-purpose register, the 32-bit IA-32 processors do not require the use\nof the 16-bit operand-size prefix (a byte with the value 66H) with\n\n| 1.| If a code instruction breakpoint (for \n| | debug) is placed on an instruction located \n| | immediately after a MOV SS instruction, \n| | the breakpoint may not be triggered. \n| | However, in a sequence of instructions \n| | that load the SS register, only the \n| | first instruction in the sequence is \n| | guaranteed to delay an interrupt. In \n| | the following sequence, interrupts may \n| | be recognized before MOV ESP, EBP executes:\n| | MOV SS, EDX MOV SS, EAX MOV ESP, EBP \nthis instruction, but most assemblers will insert it if the standard form of\nthe instruction is used (for example, MOV DS, AX). The processor will execute\nthis instruction correctly, but it will usually require an extra clock. With\nmost assemblers, using the instruction form MOV DS, EAX will avoid this unneeded\n66H prefix. When the processor executes the instruction with a 32-bit general-purpose\nregister, it assumes that the 16 least-significant bits of the general-purpose\nregister are the destination or source operand. If the register is a destination\noperand, the resulting value in the two high-order bytes of the register is\nimplementation dependent. For the Pentium 4, Intel Xeon, and P6 family processors,\nthe two high-order bytes are filled with zeros; for earlier 32-bit IA-32 processors,\nthe two high order bytes are undefined.\n\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of\nthe REX.R prefix permits access to additional registers (R8-R15). Use of the\nREX.W prefix promotes operation to 64 bits. See the summary chart at the beginning\nof this section for encoding data and limits.\n\nOperation:\n\nDEST <- SRC;\nLoading a segment register while in protected mode results in special checks and actions, as described in the\nfollowing listing. These checks are performed on the segment selector and the segment descriptor to which it\npoints.\nIF SS is loaded\n THEN\n IF segment selector is NULL\n THEN #GP(0); FI;\n IF segment selector index is outside descriptor table limits\n or segment selector's RPL != CPL\n or segment is not a writable data segment\n or DPL != CPL\n THEN #GP(selector); FI;\n IF segment not marked present\n THEN #SS(selector);\n ELSE\n SS <- segment selector;\n SS <- segment descriptor; FI;\nFI;\nIF DS, ES, FS, or GS is loaded with non-NULL selector\nTHEN\n IF segment selector index is outside descriptor table limits\n or segment is not a data or readable code segment\n or ((segment is a data or nonconforming code segment)\n or ((RPL > DPL) and (CPL > DPL))\n THEN #GP(selector); FI;\n IF segment not marked present\n THEN #NP(selector);\n ELSE\n SegmentRegister <- segment selector;\n SegmentRegister <- segment descriptor; FI;\nFI;\nIF DS, ES, FS, or GS is loaded with NULL selector\n THEN\n SegmentRegister <- segment selector;\n SegmentRegister <- segment descriptor;\nFI;\n\nFlags Affected:\nNone.\n\n\nProtected Mode Exceptions:\n| #GP(0) | If attempt is made to load SS register \n| | with NULL segment selector. If the destination\n| | operand is in a non-writable segment. \n| | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. If the DS, ES, FS, or \n| | GS register contains a NULL segment \n| | selector. \n| #GP(selector) | If segment selector index is outside \n| | descriptor table limits. If the SS register \n| | is being loaded and the segment selector's \n| | RPL and the segment descriptor's DPL \n| | are not equal to the CPL. If the SS \n| | register is being loaded and the segment \n| | pointed to is a non-writable data segment. \n| | If the DS, ES, FS, or GS register is \n| | being loaded and the segment pointed \n| | to is not a data or readable code segment. \n| | If the DS, ES, FS, or GS register is \n| | being loaded and the segment pointed \n| | to is a data or nonconforming code segment, \n| | but both the RPL and the CPL are greater \n| | than the DPL. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #SS(selector) | If the SS register is being loaded and \n| | the segment pointed to is marked not \n| | present. \n| #NP | If the DS, ES, FS, or GS register is \n| | being loaded and the segment pointed \n| | to is marked not present. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If attempt is made to load the CS register. \n| | If the LOCK prefix is used. \n\nReal-Address Mode Exceptions:\n| #GP| If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS| If a memory operand effective address \n| | is outside the SS segment limit. \n| #UD| If attempt is made to load the CS register.\n| | If the LOCK prefix is used. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0) | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made. \n| #UD | If attempt is made to load the CS register.\n| | If the LOCK prefix is used. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #GP(0) | If the memory address is in a non-canonical \n| | form. If an attempt is made to load \n| | SS register with NULL segment selector \n| | when CPL = 3. If an attempt is made \n| | to load SS register with NULL segment \n| | selector when CPL < 3 and CPL != RPL. \n| #GP(selector) | If segment selector index is outside \n| | descriptor table limits. If the memory \n| | access to the descriptor table is non-canonical.\n| | If the SS register is being loaded and \n| | the segment selector's RPL and the segment \n| | descriptor's DPL are not equal to the \n| | CPL. If the SS register is being loaded \n| | and the segment pointed to is a nonwritable \n| | data segment. If the DS, ES, FS, or \n| | GS register is being loaded and the \n| | segment pointed to is not a data or \n| | readable code segment. If the DS, ES, \n| | FS, or GS register is being loaded and \n| | the segment pointed to is a data or \n| | nonconforming code segment, but both \n| | the RPL and the CPL are greater than \n| | the DPL. \n| #SS(0) | If the stack address is in a non-canonical \n| | form. \n| #SS(selector) | If the SS register is being loaded and \n| | the segment pointed to is marked not \n| | present. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If attempt is made to load the CS register. \n| | If the LOCK prefix is used. \n\nMOV - Move to/from Control Registers:\n| Opcode/Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| 0F 20/r MOV r32, CR0-CR7 | MR | N.E. | Valid | Move control register to r32. \n| 0F 20/r MOV r64, CR0-CR7 REX.R + 0F| MR MR| Valid Valid| N.E. N.E. | Move extended control register to r64.\n| 20 /0 MOV r64, CR8 | | | | Move extended CR8 to r64.1 \n| 0F 22 /r MOV CR0-CR7, r32 | RM | N.E. | Valid | Move r32 to control register. \n| 0F 22 /r MOV CR0-CR7, r64 | RM | Valid | N.E. | Move r64 to extended control register.\n| REX.R + 0F 22 /0 MOV CR8, r64 | RM | Valid | N.E. | Move r64 to extended CR8.1 \n\nNOTE::\n| 1.| MOV CR* instructions, except for MOV \n| | CR8, are serializing instructions. MOV\n| | CR8 is not architecturally defined as \n| | a serializing instruction. For more \n| | information, see Chapter 8 in Intel\u00ae \n| | 64 and IA-32 Architectures Software \n| | Developer's Manual, Volume 3A. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n\nDescription:\nMoves the contents of a control register (CR0, CR2, CR3, CR4, or CR8) to a general-purpose\nregister or the contents of a general purpose register to a control register.\nThe operand size for these instructions is always 32 bits in non-64-bit modes,\nregardless of the operand-size attribute. (See \u201cControl Registers\u201d in Chapter\n2 of the Intel\u00ae64 and IA-32 Architectures Software Developer's Manual, Volume\n3A, for a detailed description of the flags and fields in the control registers.)\nThis instruction can be executed only when the current privilege level is 0.\n\nAt the opcode level, the reg field within the ModR/M byte specifies which of\nthe control registers is loaded or read. The 2 bits in the mod field are ignored.\nThe r/m field specifies the general-purpose register loaded or read. Attempts\nto reference CR1, CR5, CR6, CR7, and CR9-CR15 result in undefined opcode (#UD)\nexceptions.\n\nWhen loading control registers, programs should not attempt to change the reserved\nbits; that is, always set reserved bits to the value previously read. An attempt\nto change CR4's reserved bits will cause a general protection fault. Reserved\nbits in CR0 and CR3 remain clear after any load of those registers; attempts\nto set them have no impact. On Pentium 4, Intel Xeon and P6 family processors,\nCR0.ET remains set after any load of CR0; attempts to clear this bit have no\nimpact.\n\nIn certain cases, these instructions have the side effect of invalidating entries\nin the TLBs and the paging-structure caches. See Section 4.10.4.1, \u201cOperations\nthat Invalidate TLBs and Paging-Structure Caches,\u201d in the Intel\u00ae 64 and IA-32\nArchitectures Software Developer's Manual, Volume 3A for details.\n\nThe following side effects are implementation-specific for the Pentium 4, Intel\nXeon, and P6 processor family: when modifying PE or PG in register CR0, or PSE\nor PAE in register CR4, all TLB entries are flushed, including global entries.\nSoftware should not depend on this functionality in all Intel 64 or IA-32 processors.\n\nIn 64-bit mode, the instruction's default operation size is 64 bits. The REX.R\nprefix must be used to access CR8. Use of REX.B permits access to additional\nregisters (R8-R15). Use of the REX.W prefix or 66H prefix is ignored. Use of\n\nthe REX.R prefix to specify a register other than CR8 causes an invalid-opcode\nexception. See the summary chart at the beginning of this section for encoding\ndata and limits.\n\nIf CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether\nthe instruction invalidates entries in the TLBs and the paging-structure caches\n(see Section 4.10.4.1, \u201cOperations that Invalidate TLBs and Paging-Structure\nCaches,\u201d in the Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual,\nVolume 3A). The instruction does not modify bit 63 of CR3, which is reserved\nand always 0.\n\nSee \u201cChanges to Instruction Behavior in VMX Non-Root Operation\u201d in Chapter 25\nof the Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual, Volume\n3C, for more information about the behavior of this instruction in VMX non-root\noperation.\n\nOperation:\n\nDEST <- SRC;\n\nFlags Affected:\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\n\n\nProtected Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write invalid\n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0, or setting the CD flag to \n| | 0 when the NW flag is set to 1). If \n| | an attempt is made to write a 1 to any \n| | reserved bit in CR4. If an attempt is \n| | made to write 1 to CR4.PCIDE. If any \n| | of the reserved bits are set in the \n| | page-directory pointers table (PDPT) \n| | and the loading of a control register \n| | causes the PDPT to be loaded into the \n| | processor. \n| #UD | If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. \n\nReal-Address Mode Exceptions:\n| #GP| If an attempt is made to write a 1 to \n| | any reserved bit in CR4. If an attempt \n| | is made to write 1 to CR4.PCIDE. If \n| | an attempt is made to write invalid \n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0). \n| #UD| If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0)| These instructions cannot be executed\n| | in virtual-8086 mode. \n\nCompatibility Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write invalid\n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0, or setting the CD flag to \n| | 0 when the NW flag is set to 1). If \n| | an attempt is made to change CR4.PCIDE \n| | from 0 to 1 while CR3[11:0] != 000H. \n| | If an attempt is made to clear CR0.PG[bit\n| | 31] while CR4.PCIDE = 1. If an attempt \n| | is made to write a 1 to any reserved \n| | bit in CR3. If an attempt is made to \n| | leave IA-32e mode by clearing CR4.PAE[bit\n| | 5]. \n| #UD | If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. \n\n64-Bit Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write invalid\n| | bit combinations in CR0 (such as setting \n| | the PG flag to 1 when the PE flag is \n| | set to 0, or setting the CD flag to \n| | 0 when the NW flag is set to 1). If \n| | an attempt is made to change CR4.PCIDE \n| | from 0 to 1 while CR3[11:0] != 000H. \n| | If an attempt is made to clear CR0.PG[bit\n| | 31]. If an attempt is made to write \n| | a 1 to any reserved bit in CR4. If an \n| | attempt is made to write a 1 to any \n| | reserved bit in CR8. If an attempt is \n| | made to write a 1 to any reserved bit \n| | in CR3. If an attempt is made to leave \n| | IA-32e mode by clearing CR4.PAE[bit \n| | 5]. \n| #UD | If the LOCK prefix is used. If an attempt\n| | is made to access CR1, CR5, CR6, or \n| | CR7. If the REX.R prefix is used to \n| | specify a register other than CR8. \n\nMOV - Move to/from Debug Registers:\n| Opcode/Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| 0F 21/r MOV r32, DR0-DR7 | MR | N.E. | Valid | Move debug register to r32. \n| 0F 21/r MOV r64, DR0-DR7 | MR | Valid | N.E. | Move extended debug register to r64.\n| 0F 23 /r MOV DR0-DR7, r32| RM | N.E. | Valid | Move r32 to debug register. \n| 0F 23 /r MOV DR0-DR7, r64| RM | Valid | N.E. | Move r64 to extended debug register.\n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n\nDescription:\nMoves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or\nDR7) to a general-purpose register or vice versa. The operand size for these\ninstructions is always 32 bits in non-64-bit modes, regardless of the operand-size\nattribute. (See Section 17.2, \u201cDebug Registers\u201d, of the Intel\u00ae 64 and IA-32\nArchitectures Software Developer's Manual, Volume 3A, for a detailed description\nof the flags and fields in the debug registers.)\n\nThe instructions must be executed at privilege level 0 or in real-address mode.\n\nWhen the debug extension (DE) flag in register CR4 is clear, these instructions\noperate on debug registers in a manner that is compatible with Intel386 and\nIntel486 processors. In this mode, references to DR4 and DR5 refer to DR6 and\nDR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4\nand DR5 result in an undefined opcode (#UD) exception. (The CR4 register was\nadded to the IA-32 Architecture beginning with the Pentium processor.)\n\nAt the opcode level, the reg field within the ModR/M byte specifies which of\nthe debug registers is loaded or read. The two bits in the mod field are ignored.\nThe r/m field specifies the general-purpose register loaded or read.\n\nIn 64-bit mode, the instruction's default operation size is 64 bits. Use of\nthe REX.B prefix permits access to additional registers (R8-R15). Use of the\nREX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalidopcode\nexception. See the summary chart at the beginning of this section for encoding\ndata and limits.\n\nOperation:\n\nIF ((DE = 1) and (SRC or DEST = DR4 or DR5))\n THEN\n #UD;\n ELSE\n DEST <- SRC;\nFI;\n\nFlags Affected:\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\n\n\nProtected Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. \n| #UD | If CR4.DE[bit 3] = 1 (debug extensions) \n| | and a MOV instruction is executed involving\n| | DR4 or DR5. If the LOCK prefix is used. \n| #DB | If any debug register is accessed while \n| | the DR7.GD[bit 13] = 1. \n\nReal-Address Mode Exceptions:\n| #UD| If CR4.DE[bit 3] = 1 (debug extensions) \n| | and a MOV instruction is executed involving\n| | DR4 or DR5. If the LOCK prefix is used. \n| #DB| If any debug register is accessed while \n| | the DR7.GD[bit 13] = 1. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0)| The debug registers cannot be loaded\n| | or read when in virtual-8086 mode. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #GP(0)| If the current privilege level is not \n| | 0. If an attempt is made to write a \n| | 1 to any of bits 63:32 in DR6. If an \n| | attempt is made to write a 1 to any \n| | of bits 63:32 in DR7. \n| #UD | If CR4.DE[bit 3] = 1 (debug extensions) \n| | and a MOV instruction is executed involving\n| | DR4 or DR5. If the LOCK prefix is used. \n| | If the REX.R prefix is used. \n| #DB | If any debug register is accessed while \n| | the DR7.GD[bit 13] = 1. \n", "mnem": "MOV" }, { @@ -1065,7 +1053,7 @@ "mnem": "MOVBE" }, { - "description": "\nMOVD/MOVQ - Move Doubleword/Move Quadword:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| 0F 6E /r MOVD mm, r/m32 | RM | V/V | MMX | Move doubleword from r/m32 to mm. \n| REX.W + 0F 6E /r MOVQ mm, r/m64 | RM | V/N.E. | MMX | Move quadword from r/m64 to mm. \n| 0F 7E /r MOVD r/m32, mm | MR | V/V | MMX | Move doubleword from mm to r/m32. \n| REX.W + 0F 7E /r MOVQ r/m64, mm | MR | V/N.E. | MMX | Move quadword from mm to r/m64. \n| VEX.128.66.0F.W0 6E /VMOVD xmm1, r32/m32 | RM | V/V | AVX | Move doubleword from r/m32 to xmm1. \n| VEX.128.66.0F.W1 6E /r VMOVQ xmm1, r64/m64| RM | V/N.E. | AVX | Move quadword from r/m64 to xmm1. \n| 66 0F 6E /r MOVD xmm, r/m32 | RM | V/V | SSE2 | Move doubleword from r/m32 to xmm. \n| 66 REX.W 0F 6E /r MOVQ xmm, r/m64 | RM | V/N.E. | SSE2 | Move quadword from r/m64 to xmm. \n| 66 0F 7E /r MOVD r/m32, xmm | MR | V/V | SSE2 | Move doubleword from xmm register to \n| | | | | r/m32. \n| 66 REX.W 0F 7E /r MOVQ r/m64, xmm | MR | V/N.E. | SSE2 | Move quadword from xmm register to r/m64.\n| VEX.128.66.0F.W0 7E /r VMOVD r32/m32, | MR | V/V | AVX | Move doubleword from xmm1 register to \n| xmm1 | | | | r/m32. \n| VEX.128.66.0F.W1 7E /r VMOVQ r64/m64, | MR | V/N.E. | AVX | Move quadword from xmm1 register to \n| xmm1 | | | | r/m64. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n\nDescription:\nCopies a doubleword from the source operand (second operand) to the destination\noperand (first operand). The source and destination operands can be general-purpose\nregisters, MMX technology registers, XMM registers, or 32-bit memory locations.\nThis instruction can be used to move a doubleword to and from the low doubleword\nof an MMX technology register and a general-purpose register or a 32-bit memory\nlocation, or to and from the low doubleword of an XMM register and a general-purpose\nregister or a 32-bit memory location. The instruction cannot be used to transfer\ndata between MMX technology registers, between XMM registers, between general-purpose\nregisters, or between memory locations.\n\nWhen the destination operand is an MMX technology register, the source operand\nis written to the low doubleword of the register, and the register is zero-extended\nto 64 bits. When the destination operand is an XMM register, the source operand\nis written to the low doubleword of the register, and the register is zero-extended\nto 128 bits.\n\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of\nthe REX.R prefix permits access to additional registers (R8-R15). Use of the\nREX.W prefix promotes operation to 64 bits. See the summary chart at the beginning\nof this section for encoding data and limits.\n\nOperation:\n\nMOVD (when destination operand is MMX technology register)\n DEST[31:0] <- SRC;\n DEST[63:32] <- 00000000H;\nMOVD (when destination operand is XMM register)\n DEST[31:0] <- SRC;\n DEST[127:32] <- 000000000000000000000000H;\n DEST[VLMAX-1:128] (Unmodified)\nMOVD (when source operand is MMX technology or XMM register)\n DEST <- SRC[31:0];\nVMOVD (VEX-encoded version when destination is an XMM register)\n DEST[31:0] <- SRC[31:0]\n DEST[VLMAX-1:32] <- 0\nMOVQ (when destination operand is XMM register)\n DEST[63:0] <- SRC[63:0];\n DEST[127:64] <- 0000000000000000H;\n DEST[VLMAX-1:128] (Unmodified)\nMOVQ (when destination operand is r/m64)\n DEST[63:0] <- SRC[63:0];\nMOVQ (when source operand is XMM register or r/m64)\n DEST <- SRC[63:0];\nVMOVQ (VEX-encoded version when destination is an XMM register)\n DEST[63:0] <- SRC[63:0]\n DEST[VLMAX-1:64] <- 0\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVD:| __m64 _mm_cvtsi32_si64 (int i ) \n| MOVD:| int _mm_cvtsi64_si32 ( __m64m ) \n| MOVD:| __m128i _mm_cvtsi32_si128 (int a) \n| MOVD:| int _mm_cvtsi128_si32 ( __m128i a) \n| MOVQ:| __int64 _mm_cvtsi128_si64(__m128i);\n| MOVQ:| __m128i _mm_cvtsi64_si128(__int64);\n\nFlags Affected:\nNone.\n\n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Exceptions Type 5; additionally\n\n| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.\n", + "description": "\nMOVD/MOVQ - Move Doubleword/Move Quadword:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| 0F 6E /r MOVD mm, r/m32 | RM | V/V | MMX | Move doubleword from r/m32 to mm. \n| REX.W + 0F 6E /r MOVQ mm, r/m64 | RM | V/N.E. | MMX | Move quadword from r/m64 to mm. \n| 0F 7E /r MOVD r/m32, mm | MR | V/V | MMX | Move doubleword from mm to r/m32. \n| REX.W + 0F 7E /r MOVQ r/m64, mm | MR | V/N.E. | MMX | Move quadword from mm to r/m64. \n| VEX.128.66.0F.W0 6E /VMOVD xmm1, r32/m32 | RM | V/V | AVX | Move doubleword from r/m32 to xmm1. \n| VEX.128.66.0F.W1 6E /r VMOVQ xmm1, r64/m64| RM | V/N.E. | AVX | Move quadword from r/m64 to xmm1. \n| 66 0F 6E /r MOVD xmm, r/m32 | RM | V/V | SSE2 | Move doubleword from r/m32 to xmm. \n| 66 REX.W 0F 6E /r MOVQ xmm, r/m64 | RM | V/N.E. | SSE2 | Move quadword from r/m64 to xmm. \n| 66 0F 7E /r MOVD r/m32, xmm | MR | V/V | SSE2 | Move doubleword from xmm register to \n| | | | | r/m32. \n| 66 REX.W 0F 7E /r MOVQ r/m64, xmm | MR | V/N.E. | SSE2 | Move quadword from xmm register to r/m64.\n| VEX.128.66.0F.W0 7E /r VMOVD r32/m32, | MR | V/V | AVX | Move doubleword from xmm1 register to \n| xmm1 | | | | r/m32. \n| VEX.128.66.0F.W1 7E /r VMOVQ r64/m64, | MR | V/N.E. | AVX | Move quadword from xmm1 register to \n| xmm1 | | | | r/m64. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n\nDescription:\nCopies a doubleword from the source operand (second operand) to the destination\noperand (first operand). The source and destination operands can be general-purpose\nregisters, MMX technology registers, XMM registers, or 32-bit memory locations.\nThis instruction can be used to move a doubleword to and from the low doubleword\nof an MMX technology register and a general-purpose register or a 32-bit memory\nlocation, or to and from the low doubleword of an XMM register and a general-purpose\nregister or a 32-bit memory location. The instruction cannot be used to transfer\ndata between MMX technology registers, between XMM registers, between general-purpose\nregisters, or between memory locations.\n\nWhen the destination operand is an MMX technology register, the source operand\nis written to the low doubleword of the register, and the register is zero-extended\nto 64 bits. When the destination operand is an XMM register, the source operand\nis written to the low doubleword of the register, and the register is zero-extended\nto 128 bits.\n\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of\nthe REX.R prefix permits access to additional registers (R8-R15). Use of the\nREX.W prefix promotes operation to 64 bits. See the summary chart at the beginning\nof this section for encoding data and limits.\n\nOperation:\n\nMOVD (when destination operand is MMX technology register)\n DEST[31:0] <- SRC;\n DEST[63:32] <- 00000000H;\nMOVD (when destination operand is XMM register)\n DEST[31:0] <- SRC;\n DEST[127:32] <- 000000000000000000000000H;\n DEST[VLMAX-1:128] (Unmodified)\nMOVD (when source operand is MMX technology or XMM register)\n DEST <- SRC[31:0];\nVMOVD (VEX-encoded version when destination is an XMM register)\n DEST[31:0] <- SRC[31:0]\n DEST[VLMAX-1:32] <- 0\nMOVQ (when destination operand is XMM register)\n DEST[63:0] <- SRC[63:0];\n DEST[127:64] <- 0000000000000000H;\n DEST[VLMAX-1:128] (Unmodified)\nMOVQ (when destination operand is r/m64)\n DEST[63:0] <- SRC[63:0];\nMOVQ (when source operand is XMM register or r/m64)\n DEST <- SRC[63:0];\nVMOVQ (VEX-encoded version when destination is an XMM register)\n DEST[63:0] <- SRC[63:0]\n DEST[VLMAX-1:64] <- 0\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVD:| __m64 _mm_cvtsi32_si64 (int i ) \n| MOVD:| int _mm_cvtsi64_si32 ( __m64m ) \n| MOVD:| __m128i _mm_cvtsi32_si128 (int a) \n| MOVD:| int _mm_cvtsi128_si32 ( __m128i a) \n| MOVQ:| __int64 _mm_cvtsi128_si64(__m128i);\n| MOVQ:| __m128i _mm_cvtsi64_si128(__int64);\n\nFlags Affected:\nNone.\n\n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Exceptions Type 5; additionally\n\n| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.\n\nMOVQ - Move Quadword:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| 0F 6F /r MOVQ mm, mm/m64 | RM | V/V | MMX | Move quadword from mm/m64 to mm. \n| 0F 7F /r MOVQ mm/m64, mm | MR | V/V | MMX | Move quadword from mm to mm/m64. \n| F3 0F 7E /r MOVQ xmm1, xmm2/m64 | RM | V/V | SSE2 | Move quadword from xmm2/mem64 to xmm1.\n| VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1, | RM | V/V | AVX | Move quadword from xmm2 to xmm1. \n| xmm2 | | | | \n| VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1, | RM | V/V | AVX | Load quadword from m64 to xmm1. \n| m64 | | | | \n| 66 0F D6 /r MOVQ xmm2/m64, xmm1 | MR | V/V | SSE2 | Move quadword from xmm1 to xmm2/mem64.\n| VEX.128.66.0F.WIG D6 /r VMOVQ xmm1/m64,| MR | V/V | AVX | Move quadword from xmm2 register to \n| xmm2 | | | | xmm1/m64. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n\nDescription:\nCopies a quadword from the source operand (second operand) to the destination\noperand (first operand). The source and destination operands can be MMX technology\nregisters, XMM registers, or 64-bit memory locations. This instruction can be\nused to move a quadword between two MMX technology registers or between an MMX\ntechnology register and a 64-bit memory location, or to move data between two\nXMM registers or between an XMM register and a 64-bit memory location. The instruction\ncannot be used to transfer data between memory locations.\n\nWhen the source operand is an XMM register, the low quadword is moved; when\nthe destination operand is an XMM register, the quadword is stored to the low\nquadword of the register, and the high quadword is cleared to all 0s.\n\nIn 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction\nto access additional registers (XMM8-XMM15). Note: In VEX.128.66.0F D6 instruction\nversion, VEX.vvvv and VEX.L=1 are reserved and the former must be 1111b otherwise\ninstructions will #UD. Note: In VEX.128.F3.0F 7E version, VEX.vvvv and VEX.L=1\nare reserved and the former must be 1111b, otherwise instructions will #UD.\n\nOperation:\n\nMOVQ instruction when operating on MMX technology registers and memory locations:\n DEST <- SRC;\nMOVQ instruction when source and destination operands are XMM registers:\n DEST[63:0] <- SRC[63:0];\n DEST[127:64] <- 0000000000000000H;\nMOVQ instruction when source operand is XMM register and destination\noperand is memory location:\n DEST <- SRC[63:0];\nMOVQ instruction when source operand is memory location and destination\noperand is XMM register:\n DEST[63:0] <- SRC;\n DEST[127:64] <- 0000000000000000H;\nVMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\nVMOVQ (VEX.128.66.0F D6) with XMM register source and destination:\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\nVMOVQ (7E) with memory source:\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\nVMOVQ (D6) with memory dest:\nDEST[63:0] <- SRC2[63:0]\n\nFlags Affected:\nNone.\n\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVQ:| m128i _mm_mov_epi64(__m128i a)\n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Table 22-8, \u201cException Conditions for Legacy SIMD/MMX Instructions without\nFP Exception,\u201d in the Intel\u00ae 64 and IA-32 Architectures Software Developer's\nManual, Volume 3B.\n", "mnem": "MOVD" }, { @@ -1144,16 +1132,12 @@ "description": "-R:MOVD", "mnem": "MOVQ" }, - { - "description": "\nMOVQ - Move Quadword:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| 0F 6F /r MOVQ mm, mm/m64 | RM | V/V | MMX | Move quadword from mm/m64 to mm. \n| 0F 7F /r MOVQ mm/m64, mm | MR | V/V | MMX | Move quadword from mm to mm/m64. \n| F3 0F 7E /r MOVQ xmm1, xmm2/m64 | RM | V/V | SSE2 | Move quadword from xmm2/mem64 to xmm1.\n| VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1, | RM | V/V | AVX | Move quadword from xmm2 to xmm1. \n| xmm2 | | | | \n| VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1, | RM | V/V | AVX | Load quadword from m64 to xmm1. \n| m64 | | | | \n| 66 0F D6 /r MOVQ xmm2/m64, xmm1 | MR | V/V | SSE2 | Move quadword from xmm1 to xmm2/mem64.\n| VEX.128.66.0F.WIG D6 /r VMOVQ xmm1/m64,| MR | V/V | AVX | Move quadword from xmm2 register to \n| xmm2 | | | | xmm1/m64. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n\nDescription:\nCopies a quadword from the source operand (second operand) to the destination\noperand (first operand). The source and destination operands can be MMX technology\nregisters, XMM registers, or 64-bit memory locations. This instruction can be\nused to move a quadword between two MMX technology registers or between an MMX\ntechnology register and a 64-bit memory location, or to move data between two\nXMM registers or between an XMM register and a 64-bit memory location. The instruction\ncannot be used to transfer data between memory locations.\n\nWhen the source operand is an XMM register, the low quadword is moved; when\nthe destination operand is an XMM register, the quadword is stored to the low\nquadword of the register, and the high quadword is cleared to all 0s.\n\nIn 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction\nto access additional registers (XMM8-XMM15). Note: In VEX.128.66.0F D6 instruction\nversion, VEX.vvvv and VEX.L=1 are reserved and the former must be 1111b otherwise\ninstructions will #UD. Note: In VEX.128.F3.0F 7E version, VEX.vvvv and VEX.L=1\nare reserved and the former must be 1111b, otherwise instructions will #UD.\n\nOperation:\n\nMOVQ instruction when operating on MMX technology registers and memory locations:\n DEST <- SRC;\nMOVQ instruction when source and destination operands are XMM registers:\n DEST[63:0] <- SRC[63:0];\n DEST[127:64] <- 0000000000000000H;\nMOVQ instruction when source operand is XMM register and destination\noperand is memory location:\n DEST <- SRC[63:0];\nMOVQ instruction when source operand is memory location and destination\noperand is XMM register:\n DEST[63:0] <- SRC;\n DEST[127:64] <- 0000000000000000H;\nVMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\nVMOVQ (VEX.128.66.0F D6) with XMM register source and destination:\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\nVMOVQ (7E) with memory source:\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\nVMOVQ (D6) with memory dest:\nDEST[63:0] <- SRC2[63:0]\n\nFlags Affected:\nNone.\n\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVQ:| m128i _mm_mov_epi64(__m128i a)\n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Table 22-8, \u201cException Conditions for Legacy SIMD/MMX Instructions without\nFP Exception,\u201d in the Intel\u00ae 64 and IA-32 Architectures Software Developer's\nManual, Volume 3B.\n\n", - "mnem": "MOVQ" - }, { "description": "\nMOVQ2DQ - Move Quadword from MMX Technology to XMM Register:\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| F3 0F D6 /r| MOVQ2DQ xmm, mm| RM | Valid | Valid | Move quadword from mmx to low quadword\n| | | | | | of xmm. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n\nDescription:\nMoves the quadword from the source operand (second operand) to the low quadword\nof the destination operand (first operand). The source operand is an MMX technology\nregister and the destination operand is an XMM register.\n\nThis instruction causes a transition from x87 FPU to MMX technology operation\n(that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word\nis set to all 0s [valid]). If this instruction is executed while an x87 FPU\nfloating-point exception is pending, the exception is handled before the MOVQ2DQ\ninstruction is executed.\n\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional\nregisters (XMM8-XMM15).\n\nOperation:\n\nDEST[63:0] <- SRC[63:0];\nDEST[127:64] <- 00000000000000000H;\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVQ2DQ:| __128i _mm_movpi64_pi64 ( __m64 a)\n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nProtected Mode Exceptions:\n| #NM| If CR0.TS[bit 3] = 1. \n| #UD| If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit \n| | 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] \n| | = 0. If the LOCK prefix is used. \n| #MF| If there is a pending x87 FPU exception.\n\nReal-Address Mode Exceptions:\nSame exceptions as in protected mode.\n\n\nVirtual-8086 Mode Exceptions:\nSame exceptions as in protected mode.\n\n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\nSame exceptions as in protected mode.\n\n", "mnem": "MOVQ2DQ" }, { - "description": "\nMOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String:\n\\\n\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| A4 | MOVS m8, m8 | NP | Valid | Valid | For legacy mode, Move byte from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move byte from address (R|E)SI to (R|E)DI. \n| A5 | MOVS m16, m16| NP | Valid | Valid | For legacy mode, move word from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move word at address (R|E)SI to (R|E)DI. \n| A5 | MOVS m32, m32| NP | Valid | Valid | For legacy mode, move dword from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move dword from address (R|E)SI to (R|E)DI.\n| REX.W + A5| MOVS m64, m64| NP | Valid | N.E. | Move qword from address (R|E)SI to (R|E)DI.\n| A4 | MOVSB | NP | Valid | Valid | For legacy mode, Move byte from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move byte from address (R|E)SI to (R|E)DI. \n| A5 | MOVSW | NP | Valid | Valid | For legacy mode, move word from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move word at address (R|E)SI to (R|E)DI. \n| A5 | MOVSD | NP | Valid | Valid | For legacy mode, move dword from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move dword from address (R|E)SI to (R|E)DI.\n| REX.W + A5| MOVSQ | NP | Valid | N.E. | Move qword from address (R|E)SI to (R|E)DI.\n\nInstruction Operand Encoding:\n| Op/En| Operand 1| Operand 2| Operand 3| Operand 4\n| NP | NA | NA | NA | NA \n\nDescription:\nMoves the byte, word, or doubleword specified with the second operand (source\noperand) to the location specified with the first operand (destination operand).\nBoth the source and destination operands are located in memory. The address\nof the source operand is read from the DS:ESI or the DS:SI registers (depending\non the address-size attribute of the instruction, 32 or 16, respectively). The\naddress of the destination operand is read from the ES:EDI or the ES:DI registers\n(again depending on the address-size attribute of the instruction). The DS segment\nmay be overridden with a segment override prefix, but the ES segment cannot\nbe overridden.\n\nAt the assembly-code level, two forms of this instruction are allowed: the \u201cexplicit-operands\u201d\nform and the \u201cnooperands\u201d form. The explicit-operands form (specified with the\nMOVS mnemonic) allows the source and destination operands to be specified explicitly.\nHere, the source and destination operands should be symbols that indicate the\nsize and location of the source value and the destination, respectively. This\nexplicit-operands form is provided to allow documentation; however, note that\nthe documentation provided by this form can be misleading. That is, the source\nand destination operand symbols must specify the correct type (size) of the\noperands (bytes, words, or doublewords), but they do not have to specify the\ncorrect location. The locations of the source and destination operands are always\nspecified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly\nbefore the move string instruction is executed.\n\nThe no-operands form provides \u201cshort forms\u201d of the byte, word, and doubleword\nversions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed\nto be the source and destination operands, respectively. The size of the source\nand destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW\n(word move), or MOVSD (doubleword move).\n\nAfter the move operation, the (E)SI and (E)DI registers are incremented or decremented\nautomatically according to the setting of the DF flag in the EFLAGS register.\n(If the DF flag is 0, the (E)SI and (E)DI register are incre-\n\nmented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.)\nThe registers are incremented or decremented by 1 for byte operations, by 2\nfor word operations, or by 4 for doubleword operations.\n\n\nNOTE:\nTo improve performance, more recent processors support modifications to the\nprocessor's operation during the string store operations initiated with MOVS\nand MOVSB. See Section 7.3.9.3 in the Intel\u00ae 64 and IA-32 Architectures Software\nDeveloper's Manual, Volume 1 for additional information on fast-string operation.\n\nThe MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix\n(see \u201cREP/REPE/REPZ /REPNE/REPNZ - Repeat String Operation Prefix\u201d in Chapter\n4 of the Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual, Volume\n2B, for a description of the REP prefix) for block moves of ECX bytes, words,\nor doublewords.\n\nIn 64-bit mode, the instruction's default address size is 64 bits, 32-bit address\nsize is supported using the prefix 67H. The 64-bit addresses are specified by\nRSI and RDI; 32-bit address are specified by ESI and EDI. Use of the REX.W prefix\npromotes doubleword operation to 64 bits. See the summary chart at the beginning\nof this section for encoding data and limits.\n\nOperation:\n\nDEST <- SRC;\nNon-64-bit Mode:\nIF (Byte move)\n THEN IF DF = 0\n THEN\n (E)SI <- (E)SI + 1;\n (E)DI <- (E)DI + 1;\n ELSE\n (E)SI <- (E)SI - 1;\n (E)DI <- (E)DI - 1;\n FI;\n ELSE IF (Word move)\n THEN IF DF = 0\n (E)SI <- (E)SI + 2;\n (E)DI <- (E)DI + 2;\n FI;\n ELSE\n (E)SI <- (E)SI - 2;\n (E)DI <- (E)DI - 2;\n FI;\n ELSE IF (Doubleword move)\n THEN IF DF = 0\n (E)SI <- (E)SI + 4;\n (E)DI <- (E)DI + 4;\n FI;\n ELSE\n (E)SI <- (E)SI - 4;\n (E)DI <- (E)DI - 4;\n FI;\nFI;\n64-bit Mode:\nIF (Byte move)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 1;\n (R|E)DI <- (R|E)DI + 1;\n ELSE\n (R|E)SI <- (R|E)SI - 1;\n (R|E)DI <- (R|E)DI - 1;\n FI;\n ELSE IF (Word move)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 2;\n (R|E)DI <- (R|E)DI + 2;\n FI;\n ELSE\n (R|E)SI <- (R|E)SI - 2;\n (R|E)DI <- (R|E)DI - 2;\n FI;\n ELSE IF (Doubleword move)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 4;\n (R|E)DI <- (R|E)DI + 4;\n FI;\n ELSE\n (R|E)SI <- (R|E)SI - 4;\n (R|E)DI <- (R|E)DI - 4;\n FI;\n ELSE IF (Quadword move)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 8;\n (R|E)DI <- (R|E)DI + 8;\n FI;\n ELSE\n (R|E)SI <- (R|E)SI - 8;\n (R|E)DI <- (R|E)DI - 8;\n FI;\nFI;\n\nFlags Affected:\nNone.\n\n\nProtected Mode Exceptions:\n| #GP(0) | If the destination is located in a non-writable\n| | segment. If a memory operand effective \n| | address is outside the CS, DS, ES, FS, \n| | or GS segment limit. If the DS, ES, \n| | FS, or GS register contains a NULL segment \n| | selector. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n\nReal-Address Mode Exceptions:\n| #GP| If a memory operand effective address\n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS| If a memory operand effective address\n| | is outside the SS segment limit. \n| #UD| If the LOCK prefix is used. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0) | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made.\n| #UD | If the LOCK prefix is used. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #SS(0) | If a memory address referencing the \n| | SS segment is in a non-canonical form. \n| #GP(0) | If the memory address is in a non-canonical\n| | form. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n", + "description": "\nMOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String:\n\\\n\n| Opcode | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description \n| A4 | MOVS m8, m8 | NP | Valid | Valid | For legacy mode, Move byte from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move byte from address (R|E)SI to (R|E)DI. \n| A5 | MOVS m16, m16| NP | Valid | Valid | For legacy mode, move word from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move word at address (R|E)SI to (R|E)DI. \n| A5 | MOVS m32, m32| NP | Valid | Valid | For legacy mode, move dword from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move dword from address (R|E)SI to (R|E)DI.\n| REX.W + A5| MOVS m64, m64| NP | Valid | N.E. | Move qword from address (R|E)SI to (R|E)DI.\n| A4 | MOVSB | NP | Valid | Valid | For legacy mode, Move byte from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move byte from address (R|E)SI to (R|E)DI. \n| A5 | MOVSW | NP | Valid | Valid | For legacy mode, move word from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move word at address (R|E)SI to (R|E)DI. \n| A5 | MOVSD | NP | Valid | Valid | For legacy mode, move dword from address \n| | | | | | DS:(E)SI to ES:(E)DI. For 64-bit mode \n| | | | | | move dword from address (R|E)SI to (R|E)DI.\n| REX.W + A5| MOVSQ | NP | Valid | N.E. | Move qword from address (R|E)SI to (R|E)DI.\n\nInstruction Operand Encoding:\n| Op/En| Operand 1| Operand 2| Operand 3| Operand 4\n| NP | NA | NA | NA | NA \n\nDescription:\nMoves the byte, word, or doubleword specified with the second operand (source\noperand) to the location specified with the first operand (destination operand).\nBoth the source and destination operands are located in memory. The address\nof the source operand is read from the DS:ESI or the DS:SI registers (depending\non the address-size attribute of the instruction, 32 or 16, respectively). The\naddress of the destination operand is read from the ES:EDI or the ES:DI registers\n(again depending on the address-size attribute of the instruction). The DS segment\nmay be overridden with a segment override prefix, but the ES segment cannot\nbe overridden.\n\nAt the assembly-code level, two forms of this instruction are allowed: the \u201cexplicit-operands\u201d\nform and the \u201cnooperands\u201d form. The explicit-operands form (specified with the\nMOVS mnemonic) allows the source and destination operands to be specified explicitly.\nHere, the source and destination operands should be symbols that indicate the\nsize and location of the source value and the destination, respectively. This\nexplicit-operands form is provided to allow documentation; however, note that\nthe documentation provided by this form can be misleading. That is, the source\nand destination operand symbols must specify the correct type (size) of the\noperands (bytes, words, or doublewords), but they do not have to specify the\ncorrect location. The locations of the source and destination operands are always\nspecified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly\nbefore the move string instruction is executed.\n\nThe no-operands form provides \u201cshort forms\u201d of the byte, word, and doubleword\nversions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed\nto be the source and destination operands, respectively. The size of the source\nand destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW\n(word move), or MOVSD (doubleword move).\n\nAfter the move operation, the (E)SI and (E)DI registers are incremented or decremented\nautomatically according to the setting of the DF flag in the EFLAGS register.\n(If the DF flag is 0, the (E)SI and (E)DI register are incre-\n\nmented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.)\nThe registers are incremented or decremented by 1 for byte operations, by 2\nfor word operations, or by 4 for doubleword operations.\n\n\nNOTE:\nTo improve performance, more recent processors support modifications to the\nprocessor's operation during the string store operations initiated with MOVS\nand MOVSB. See Section 7.3.9.3 in the Intel\u00ae 64 and IA-32 Architectures Software\nDeveloper's Manual, Volume 1 for additional information on fast-string operation.\n\nThe MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix\n(see \u201cREP/REPE/REPZ /REPNE/REPNZ - Repeat String Operation Prefix\u201d in Chapter\n4 of the Intel\u00ae 64 and IA-32 Architectures Software Developer's Manual, Volume\n2B, for a description of the REP prefix) for block moves of ECX bytes, words,\nor doublewords.\n\nIn 64-bit mode, the instruction's default address size is 64 bits, 32-bit address\nsize is supported using the prefix 67H. The 64-bit addresses are specified by\nRSI and RDI; 32-bit address are specified by ESI and EDI. Use of the REX.W prefix\npromotes doubleword operation to 64 bits. See the summary chart at the beginning\nof this section for encoding data and limits.\n\nOperation:\n\nDEST <- SRC;\nNon-64-bit Mode:\nIF (Byte move)\n THEN IF DF = 0\n THEN\n (E)SI <- (E)SI + 1;\n (E)DI <- (E)DI + 1;\n ELSE\n (E)SI <- (E)SI - 1;\n (E)DI <- (E)DI - 1;\n FI;\n ELSE IF (Word move)\n THEN IF DF = 0\n (E)SI <- (E)SI + 2;\n (E)DI <- (E)DI + 2;\n FI;\n ELSE\n (E)SI <- (E)SI - 2;\n (E)DI <- (E)DI - 2;\n FI;\n ELSE IF (Doubleword move)\n THEN IF DF = 0\n (E)SI <- (E)SI + 4;\n (E)DI <- (E)DI + 4;\n FI;\n ELSE\n (E)SI <- (E)SI - 4;\n (E)DI <- (E)DI - 4;\n FI;\nFI;\n64-bit Mode:\nIF (Byte move)\n THEN IF DF = 0\n THEN\n (R|E)SI <- (R|E)SI + 1;\n (R|E)DI <- (R|E)DI + 1;\n ELSE\n (R|E)SI <- (R|E)SI - 1;\n (R|E)DI <- (R|E)DI - 1;\n FI;\n ELSE IF (Word move)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 2;\n (R|E)DI <- (R|E)DI + 2;\n FI;\n ELSE\n (R|E)SI <- (R|E)SI - 2;\n (R|E)DI <- (R|E)DI - 2;\n FI;\n ELSE IF (Doubleword move)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 4;\n (R|E)DI <- (R|E)DI + 4;\n FI;\n ELSE\n (R|E)SI <- (R|E)SI - 4;\n (R|E)DI <- (R|E)DI - 4;\n FI;\n ELSE IF (Quadword move)\n THEN IF DF = 0\n (R|E)SI <- (R|E)SI + 8;\n (R|E)DI <- (R|E)DI + 8;\n FI;\n ELSE\n (R|E)SI <- (R|E)SI - 8;\n (R|E)DI <- (R|E)DI - 8;\n FI;\nFI;\n\nFlags Affected:\nNone.\n\n\nProtected Mode Exceptions:\n| #GP(0) | If the destination is located in a non-writable\n| | segment. If a memory operand effective \n| | address is outside the CS, DS, ES, FS, \n| | or GS segment limit. If the DS, ES, \n| | FS, or GS register contains a NULL segment \n| | selector. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n\nReal-Address Mode Exceptions:\n| #GP| If a memory operand effective address\n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS| If a memory operand effective address\n| | is outside the SS segment limit. \n| #UD| If the LOCK prefix is used. \n\nVirtual-8086 Mode Exceptions:\n| #GP(0) | If a memory operand effective address \n| | is outside the CS, DS, ES, FS, or GS \n| | segment limit. \n| #SS(0) | If a memory operand effective address \n| | is outside the SS segment limit. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made.\n| #UD | If the LOCK prefix is used. \n\nCompatibility Mode Exceptions:\nSame exceptions as in protected mode.\n\n\n64-Bit Mode Exceptions:\n| #SS(0) | If a memory address referencing the \n| | SS segment is in a non-canonical form. \n| #GP(0) | If the memory address is in a non-canonical\n| | form. \n| #PF(fault-code)| If a page fault occurs. \n| #AC(0) | If alignment checking is enabled and \n| | an unaligned memory reference is made \n| | while the current privilege level is \n| | 3. \n| #UD | If the LOCK prefix is used. \n\nMOVSD - Move Scalar Double-Precision Floating-Point Value:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| F2 0F 10 /r MOVSD xmm1, xmm2/m64 | RM | V/V | SSE2 | Move scalar double-precision floating-point \n| | | | | value from xmm2/m64 to xmm1 register. \n| VEX.NDS.LIG.F2.0F.WIG 10 /r VMOVSD xmm1,| RVM | V/V | AVX | Merge scalar double-precision floating-point\n| xmm2, xmm3 | | | | value from xmm2 and xmm3 to xmm1 register. \n| VEX.LIG.F2.0F.WIG 10 /r VMOVSD xmm1, | XM | V/V | AVX | Load scalar double-precision floating-point \n| m64 | | | | value from m64 to xmm1 register. \n| F2 0F 11 /r MOVSD xmm2/m64, xmm1 | MR | V/V | SSE2 | Move scalar double-precision floating-point \n| | | | | value from xmm1 register to xmm2/m64. \n| VEX.NDS.LIG.F2.0F.WIG 11 /r VMOVSD xmm1,| MVR | V/V | AVX | Merge scalar double-precision floating-point\n| xmm2, xmm3 | | | | value from xmm2 and xmm3 registers to \n| | | | | xmm1. \n| VEX.LIG.F2.0F.WIG 11 /r VMOVSD m64, | MR | V/V | AVX | Move scalar double-precision floating-point \n| xmm1 | | | | value from xmm1 register to m64. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3 | Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| RVM | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA \n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n| XM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| MVR | ModRM:r/m (w)| VEX.vvvv (r) | ModRM:reg (r)| NA \n\nDescription:\nMOVSD moves a scalar double-precision floating-point value from the source operand\n(second operand) to the destination operand (first operand). The source and\ndestination operands can be XMM registers or 64-bit memory locations. This instruction\ncan be used to move a double-precision floating-point value to and from the\nlow quadword of an XMM register and a 64-bit memory location, or to move a double-precision\nfloating-point value between the low quadwords of two XMM registers. The instruction\ncannot be used to transfer data between memory locations. For non-VEX encoded\ninstruction syntax and when the source and destination operands are XMM registers,\nthe high quadword of the destination operand remains unchanged. When the source\noperand is a memory location and destination operand is an XMM registers, the\nhigh quadword of the destination operand is cleared to all 0s.\n\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional\nregisters (XMM8-XMM15). Note: For the \u201cVMOVSD m64, xmm1\u201d (memory store form)\ninstruction version, VEX.vvvv is reserved and must be 1111b, otherwise instruction\nwill #UD. Note: For the \u201cVMOVSD xmm1, m64\u201d (memory load form) instruction version,\nVEX.vvvv is reserved and must be 1111b otherwise instruction will #UD. VEX encoded\ninstruction syntax supports two source operands and a destination operand if\nModR/M.mod field is 11B. VEX.vvvv is used to encode the first source operand\n(the second operand). The low 128 bits of the destination operand stores the\nresult of merging the low quadword of the second source operand with the quad\nword in bits 127:64 of the first source operand. The upper bits of the destination\noperand are cleared.\n\nOperation:\n\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] (Unmodified)\nMOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)\nDEST[63:0] <- SRC[63:0]\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)\nDEST[63:0] <- SRC[63:0]\nDEST[127:64] <- 0\nDEST[VLMAX-1:128] (Unmodified)\nVMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)\nDEST[63:0] <- SRC2[63:0]\nDEST[127:64] <- SRC1[127:64]\nDEST[VLMAX-1:128] <- 0\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)\nDEST[63:0] <- SRC2[63:0]\nDEST[127:64] <- SRC1[127:64]\nDEST[VLMAX-1:128] <- 0\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVSD:| __m128d _mm_load_sd (double *p) \n| MOVSD:| void _mm_store_sd (double *p, __m128d \n| | a) \n| MOVSD:| __m128d _mm_store_sd (__m128d a, __m128d\n| | b) \n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Exceptions Type 5; additionally\n\n| #UD| If VEX.vvvv != 1111B. \n", "mnem": "MOVS" }, { @@ -1164,10 +1148,6 @@ "description": "-R:MOVS", "mnem": "MOVSD" }, - { - "description": "\nMOVSD - Move Scalar Double-Precision Floating-Point Value:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| F2 0F 10 /r MOVSD xmm1, xmm2/m64 | RM | V/V | SSE2 | Move scalar double-precision floating-point \n| | | | | value from xmm2/m64 to xmm1 register. \n| VEX.NDS.LIG.F2.0F.WIG 10 /r VMOVSD xmm1,| RVM | V/V | AVX | Merge scalar double-precision floating-point\n| xmm2, xmm3 | | | | value from xmm2 and xmm3 to xmm1 register. \n| VEX.LIG.F2.0F.WIG 10 /r VMOVSD xmm1, | XM | V/V | AVX | Load scalar double-precision floating-point \n| m64 | | | | value from m64 to xmm1 register. \n| F2 0F 11 /r MOVSD xmm2/m64, xmm1 | MR | V/V | SSE2 | Move scalar double-precision floating-point \n| | | | | value from xmm1 register to xmm2/m64. \n| VEX.NDS.LIG.F2.0F.WIG 11 /r VMOVSD xmm1,| MVR | V/V | AVX | Merge scalar double-precision floating-point\n| xmm2, xmm3 | | | | value from xmm2 and xmm3 registers to \n| | | | | xmm1. \n| VEX.LIG.F2.0F.WIG 11 /r VMOVSD m64, | MR | V/V | AVX | Move scalar double-precision floating-point \n| xmm1 | | | | value from xmm1 register to m64. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3 | Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| RVM | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA \n| MR | ModRM:r/m (w)| ModRM:reg (r)| NA | NA \n| XM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n| MVR | ModRM:r/m (w)| VEX.vvvv (r) | ModRM:reg (r)| NA \n\nDescription:\nMOVSD moves a scalar double-precision floating-point value from the source operand\n(second operand) to the destination operand (first operand). The source and\ndestination operands can be XMM registers or 64-bit memory locations. This instruction\ncan be used to move a double-precision floating-point value to and from the\nlow quadword of an XMM register and a 64-bit memory location, or to move a double-precision\nfloating-point value between the low quadwords of two XMM registers. The instruction\ncannot be used to transfer data between memory locations. For non-VEX encoded\ninstruction syntax and when the source and destination operands are XMM registers,\nthe high quadword of the destination operand remains unchanged. When the source\noperand is a memory location and destination operand is an XMM registers, the\nhigh quadword of the destination operand is cleared to all 0s.\n\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional\nregisters (XMM8-XMM15). Note: For the \u201cVMOVSD m64, xmm1\u201d (memory store form)\ninstruction version, VEX.vvvv is reserved and must be 1111b, otherwise instruction\nwill #UD. Note: For the \u201cVMOVSD xmm1, m64\u201d (memory load form) instruction version,\nVEX.vvvv is reserved and must be 1111b otherwise instruction will #UD. VEX encoded\ninstruction syntax supports two source operands and a destination operand if\nModR/M.mod field is 11B. VEX.vvvv is used to encode the first source operand\n(the second operand). The low 128 bits of the destination operand stores the\nresult of merging the low quadword of the second source operand with the quad\nword in bits 127:64 of the first source operand. The upper bits of the destination\noperand are cleared.\n\nOperation:\n\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] (Unmodified)\nMOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)\nDEST[63:0] <- SRC[63:0]\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)\nDEST[63:0] <- SRC[63:0]\nDEST[127:64] <- 0\nDEST[VLMAX-1:128] (Unmodified)\nVMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)\nDEST[63:0] <- SRC2[63:0]\nDEST[127:64] <- SRC1[127:64]\nDEST[VLMAX-1:128] <- 0\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)\nDEST[63:0] <- SRC2[63:0]\nDEST[127:64] <- SRC1[127:64]\nDEST[VLMAX-1:128] <- 0\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)\nDEST[63:0] <- SRC[63:0]\nDEST[VLMAX-1:64] <- 0\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| MOVSD:| __m128d _mm_load_sd (double *p) \n| MOVSD:| void _mm_store_sd (double *p, __m128d \n| | a) \n| MOVSD:| __m128d _mm_store_sd (__m128d a, __m128d\n| | b) \n\nSIMD Floating-Point Exceptions:\nNone.\n\n\nOther Exceptions:\nSee Exceptions Type 5; additionally\n\n| #UD| If VEX.vvvv != 1111B.\n", - "mnem": "MOVSD" - }, { "description": "\nMOVSHDUP - Move Packed Single-FP High and Duplicate:\n| Opcode/Instruction | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description \n| F3 0F 16 /r MOVSHDUP xmm1, xmm2/m128 | RM | V/V | SSE3 | Move two single-precision floating-point \n| | | | | values from the higher 32-bit operand \n| | | | | of each qword in xmm2/m128 to xmm1 and \n| | | | | duplicate each 32-bit operand to the \n| | | | | lower 32-bits of each qword. \n| VEX.128.F3.0F.WIG 16 /r VMOVSHDUP xmm1,| RM | V/V | AVX | Move odd index single-precision floating-point\n| xmm2/m128 | | | | values from xmm2/mem and duplicate each \n| | | | | element into xmm1. \n| VEX.256.F3.0F.WIG 16 /r VMOVSHDUP ymm1,| RM | V/V | AVX | Move odd index single-precision floating-point\n| ymm2/m256 | | | | values from ymm2/mem and duplicate each \n| | | | | element into ymm1. \n\nInstruction Operand Encoding:\n| Op/En| Operand 1 | Operand 2 | Operand 3| Operand 4\n| RM | ModRM:reg (w)| ModRM:r/m (r)| NA | NA \n\nDescription:\nThe linear address corresponds to the address of the least-significant byte\nof the referenced memory data. When a memory address is indicated, the 16 bytes\nof data at memory location m128 are loaded and the single-precision elements\nin positions 1 and 3 are duplicated. When the register-register form of this\noperation is used, the same operation is performed but with data coming from\nthe 128-bit source register. See Figure 3-25.\n\nMOVSHDUP xmm1, xmm2/m128\n\nxmm2/\n\n| [127:96]xmm2/| [95:64]xmm1[95:64]xmm2/m128[127:96]| [63:32]xmm1[63:32]xmm2/m128[63:32]| [31:0]m128 xmm1[31:0]RESULT: xmm2/xmm1\n| | | | m128[63:32] \n| [127:96] | [95:64] | [63:32] | [31:0] \nOM15998\n\n| Figure 3-25.| MOVSHDUP - Move Packed Single-FP High\n| | and Duplicate \nIn 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction\nto access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: Bits\n(VLMAX-1:128) of the corresponding YMM destination register remain unchanged.\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register\nare zeroed. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be\n1111b otherwise instructions will #UD.\n\nOperation:\n\nMOVSHDUP (128-bit Legacy SSE version)\nDEST[31:0] <- SRC[63:32]\nDEST[63:32] <- SRC[63:32]\nDEST[95:64] <- SRC[127:96]\nDEST[127:96] <- SRC[127:96]\nDEST[VLMAX-1:128] (Unmodified)\nVMOVSHDUP (VEX.128 encoded version)\nDEST[31:0] <- SRC[63:32]\nDEST[63:32] <- SRC[63:32]\nDEST[95:64] <- SRC[127:96]\nDEST[127:96] <- SRC[127:96]\nDEST[VLMAX-1:128] <- 0\nVMOVSHDUP (VEX.256 encoded version)\nDEST[31:0] <- SRC[63:32]\nDEST[63:32] <- SRC[63:32]\nDEST[95:64] <- SRC[127:96]\nDEST[127:96] <- SRC[127:96]\nDEST[159:128] <- SRC[191:160]\nDEST[191:160] <- SRC[191:160]\nDEST[223:192] <- SRC[255:224]\nDEST[255:224] <- SRC[255:224]\n\nIntel C/C++ Compiler Intrinsic Equivalent:\n| (V)MOVSHDUP:| __m128 _mm_movehdup_ps(__m128 a) \n| VMOVSHDUP: | __m256 _mm256_movehdup_ps (__m256 a);\n\nExceptions:\nGeneral protection exception if not aligned on 16-byte boundary, regardless\nof segment.\n\n\nNumeric Exceptions:\nNone\n\n\nOther Exceptions:\nSee Exceptions Type 2.\n\n", "mnem": "MOVSHDUP"